Correct the shift used to select condition bits and correctly compute the
branch offset.

Sign extension shift had an off-by-one error so the sign bit was not being
properly extended.

T4 encodings of unconditional branches were not being interpreted correctly
(#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits
selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for
these instructions.

in fact the decoder should _never_ panic. included here are tests that
cover the entire 32-bit instruction space and ensure that decoding and
display do not panic. these tests run uncomfortably slowly (1168s to
decode the 4b "instruction" sequences on my desktop), but verify that
panics are no longer an issue.

instead of trying to shoehorn in `adr reg, label` syntax like the manual
requests, it's much easier to just describe these as `{add, sub} reg,
pc, offset` and potentially rewrite `pc, offset` as an `adr reg, label`
if a higher-level tool has that kind of information available.