system control register names, more cleanup

3 files changed, 26 insertions, 23 deletions

diff --git a/src/display.rs b/src/display.rs
index 0c8e366..b17cc90 100644
--- a/src/display.rs
+++ b/src/display.rs
@@ -279,7 +279,7 @@ impl fmt::Display for Instruction {
                 Some(AssignMode::SetBit) => ("= setbit", true),
             };
             write!(f, "{}({}){} {}{}{}{}",
-                self.opcode, self.dest.expect("TODO: unreachable; store has a destination"),
+                self.opcode, self.dest.expect("unreachable; store has a destination"),
                 match self.flags.threads {
                     Some(DomainHint::Same) => { ":st" },
                     Some(DomainHint::All) => { ":at" },
@@ -293,15 +293,14 @@ impl fmt::Display for Instruction {
             return Ok(());
         }
 
-        // TODO: do store conditionals have assign_merge?
         static SC_STORES: &[Opcode] = &[
             Opcode::MemwStoreCond, Opcode::MemdStoreCond,
         ];
         if SC_STORES.contains(&self.opcode) {
             write!(f, "{}({}, {}) = {}",
                 self.opcode,
-                self.dest.expect("TODO: unreachable; store has a destination"),
-                self.alt_dest.expect("TODO: unreachable; store-conditional has a predicate reg"),
+                self.dest.expect("unreachable; store has a destination"),
+                self.alt_dest.expect("unreachable; store-conditional has a predicate reg"),
                 self.sources[0]
             )?;
             return Ok(());
@@ -328,7 +327,7 @@ impl fmt::Display for Instruction {
                 None => { "" },
             };
             write!(f, "if ({}({}, {})) jump{} {}",
-                self.opcode.cmp_str().unwrap(), // TODO: unwrap_unchecked??
+                self.opcode.cmp_str().unwrap(), // (obvious, but) decoder bug if this fails
                 self.sources[0],
                 self.sources[1],
                 hint_label,
@@ -953,19 +952,26 @@ impl fmt::Display for Operand {
                 f.write_str(CR_NAMES[*reg as usize])
             }
             Operand::Sr { reg } => {
-                // TODO: System control register transfer
-                // from v62
-                match reg {
-                    0 => {
-                        f.write_str("sgp0")
-                    }
-                    1 => {
-                        f.write_str("sgp1")
-                    }
-                    reg => {
-                        write!(f, "S{}", reg)
-                    }
-                }
+                // V62 "System control register transfer" includes this table
+                static SR_NAMES: [&'static str; 64] = [
+                    "sgp0", "sgp1", "stid", "elr",
+                    "badva0", "badva1", "ssr", "ccr",
+                    "htid", "badva", "imask", "S11",
+                    "S12", "S13", "S14", "S15",
+                    "evb", "modectl", "syscfg", "S19",
+                    "ipend", "vid", "iad", "S23",
+                    "iel", "S25", "iahl", "cfgbase",
+                    "diag", "rev", "pcyclelo", "pcyclehi",
+                    "isdbst", "isdbcfg0", "isdbcfg1", "S35",
+                    "brkptpc0", "brkptcfg0", "brkptpc1", "brkptcfg1",
+                    "isdbmbxin", "isdbmbxout", "isdben", "isdbgpr",
+                    "S44", "S45", "S46", "S47",
+                    "pmunct0", "pmucnt1", "pmucnt2", "pmucnt3",
+                    "pmuevtcfg", "pmucfg", "S54", "S55",
+                    "S56", "S57", "S58", "S59",
+                    "S60", "S61", "S62", "S63",
+                ];
+                f.write_str(SR_NAMES[*reg as usize])
             }
             Operand::GprNew { reg } => {
                 write!(f, "R{}.new", reg)
diff --git a/src/lib.rs b/src/lib.rs
index 6e64f97..dcb99fb 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -6518,9 +6518,6 @@ fn decode_instruction<
                 0b1101 => {
                     // 1110|1101
                     opcode_check!(inst & 0b0010_0000_0000_0000 == 0);
-                    // TODO: can remove probably?
-                    let op_lo = ((inst >> 5) & 0b111) as u8;
-                    let op_hi = ((inst >> 21) & 0b111) as u8;
 
                     handler.on_dest_decoded(Operand::gpr(reg_b0(inst)))?;
                     handler.on_source_decoded(Operand::gpr(reg_b16(inst)))?;
diff --git a/tests/from_brain.rs b/tests/from_brain.rs
index df6880a..6a5dd17 100644
--- a/tests/from_brain.rs
+++ b/tests/from_brain.rs
@@ -48,10 +48,10 @@ fn supervisor() {
     test_display(&0b0110_11_10011_00110_11_0_00010_011_10110u32.to_le_bytes(), "{ R22 = iassignr(R6) }");
 
     // ok
-    test_display(&0b0110_0111000_00010_11_0011010_0000110u32.to_le_bytes(), "{ S6 = R2 }");
+    test_display(&0b0110_0111000_00010_11_0011010_0000110u32.to_le_bytes(), "{ ssr = R2 }");
     test_display(&0b0110_1101000_00010_11_0011010_0000110u32.to_le_bytes(), "{ S7:6 = R3:2 }");
 
-    test_display(&0b0110_11101_0100010_11_000000000_00110u32.to_le_bytes(), "{ R6 = S34 }");
+    test_display(&0b0110_11101_0100010_11_000000000_00110u32.to_le_bytes(), "{ R6 = isdbcfg1 }");
     test_display(&0b0110_11110_0100010_11_000000000_00110u32.to_le_bytes(), "{ R7:6 = S35:34 }");
 
     test_display(&0b0110_1100000_00010_11_0_01101_00000000u32.to_le_bytes(), "{ tlbw(R3:2, R13) }");