yaxpeax-x86/fuzz/fuzz_targets, branch inst-behavior yaxpeax x86 decoder justify the current max instruction length 2024-06-24T21:27:25+00:00 iximeow me@iximeow.net 2024-06-24T21:06:22+00:00 dd8bd5ce0772b08c271205508e48e98ef1c58ea8 this is also checked by a new fuzz target 
this is also checked by a new fuzz target
update yaxpeax-arch to 0.3.1, fix fuzz target warnings 2024-06-24T06:25:46+00:00 iximeow me@iximeow.net 2024-06-24T06:13:03+00:00 238d65c98b2983f87c89f78a793ba7c56dcf7b01 






InstructionTextBuffer for all three modes, adjust fuzzer to match
2024-06-23T22:28:50+00:00

iximeow
me@iximeow.net

2024-06-23T22:28:50+00:00

9d9bb9b8fbc5a04f40b927093cd3ba8e562f941d












fix incorrect register class names in long_mode
2023-12-16T23:54:25+00:00

iximeow
me@iximeow.net

2023-12-16T23:54:13+00:00

83b12fc09a69cc5324f6f002b8c52382d4b236d1

also adjust changelog for a 1.2.1 version again, no new interfaces to go
with these bugfixes.





also adjust changelog for a 1.2.1 version again, no new interfaces to go
with these bugfixes.







fix opportunity for unhandled register synonyms
2023-12-16T21:26:48+00:00

iximeow
me@iximeow.net

2023-12-16T21:26:48+00:00

110f797005cca70e18cbcc0975397d26d8045245

registers `al`, `cl`, `dl`, and `bl` could have two different
representations - with `rex.w` and without. these two forms of `RegSpec`
would not compare equal, nor has the same, so for code relying on
`RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these
synonyms would introduce bugs in register analysis.

for example, in `yaxpeax-core`, this would result in instructions
writing to `rex.w al` not being visible as definitions for a future
read of `!rex.w al`.

fix this in `x86_64` code, add new test cases about the confusion,
adjust register names to make this situation more clearly a bug, and
introduce two new fuzz targets that would have helped spot this error.





registers `al`, `cl`, `dl`, and `bl` could have two different
representations - with `rex.w` and without. these two forms of `RegSpec`
would not compare equal, nor has the same, so for code relying on
`RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these
synonyms would introduce bugs in register analysis.

for example, in `yaxpeax-core`, this would result in instructions
writing to `rex.w al` not being visible as definitions for a future
read of `!rex.w al`.

fix this in `x86_64` code, add new test cases about the confusion,
adjust register names to make this situation more clearly a bug, and
introduce two new fuzz targets that would have helped spot this error.







fuzz DisplayStyle::C and fix corresponding issues
2022-01-12T23:46:39+00:00

iximeow
me@iximeow.net

2022-01-12T23:46:39+00:00

e80b5622ec956a92f24ce6487fb0d76e9c541515












add in-tree cargo fuzz targets for decode and display impls
2021-12-19T19:32:43+00:00

iximeow
me@iximeow.net

2021-12-19T19:32:43+00:00

26e019cc3788b6bac73969dc3d1753e883961339