yaxpeax-x86/src/long_mode, branch 0.0.9yaxpeax x86 decoderhttp://git.iximeow.net/yaxpeax-x86/atom?h=0.0.92020-02-23T00:59:39Zexplicitly report x87 as not (yet) supported2020-02-23T00:59:39Ziximeowme@iximeow.net2020-02-23T00:42:14Zurn:sha1:a2d4713dcae92cc16838c43f3a5e9703a1c926dasupport most avx operand codes2020-02-23T00:21:03Ziximeowme@iximeow.net2020-02-23T00:21:03Zurn:sha1:f3d8bb582c1c3e97d8002975a3da6223b263b40f
avx is still incomplete, but less so
avx is still practically untested
fix {jmp,call} <reg>, as well as jmpf/callf2020-02-22T23:38:41Ziximeowme@iximeow.net2020-02-22T23:38:41Zurn:sha1:802679e4f8362d3c819b83223854c638cc8f2b7f
also support vmxon to finish out the f30f opcode map
add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't
provide a way to distinguish different operand sizes (yet)
more sse/sse2 support2020-02-22T23:12:37Ziximeowme@iximeow.net2020-02-22T23:12:37Zurn:sha1:d1787896dacc4821ebf399508472b3985ab2a232
largely f20f/f30f opcode map items
support 660f sse2 instructions2020-02-22T08:52:38Ziximeowme@iximeow.net2020-02-22T08:51:30Zurn:sha1:33c520341b373ac18e7924eb9227615ac65c2618
this isn't quite all of sse2, but gets close. the f20f opcode map still
needs some touching up.
also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
embarassingly had OperandSpec variants for modrm displacement == 0 backwards2020-02-16T10:02:32Ziximeowme@iximeow.net2020-02-16T10:02:32Zurn:sha1:78d0c21c475fce65c36e64a36c26c689bee0faaesupport `in` and `out` instructions2020-02-11T09:00:34Ziximeowme@iximeow.net2020-02-11T09:00:34Zurn:sha1:0c1d6fc73c90f906aa2ed5dbdde1ade153e6a0adadd `RegSpec::name` to get `&'static str` labels for registers2020-02-11T08:22:16Ziximeowme@iximeow.net2020-02-11T08:22:16Zurn:sha1:bd9ae00ba84275c9414298d016da21e8106cda36derive Ord and PartialOrd for RegSpec and RegisterBank2020-02-11T08:12:45Ziximeowme@iximeow.net2020-02-11T08:12:45Zurn:sha1:f08c8bbf9f180283490fc7a4e116e8fa0ffcc681
this makes these usable as keys in collections such as BTreeMap. there
is no specific ordering imposed by Ord (f.ex it may be the case that
`eax > dx` while `eax > rax`), but some specific ordering may be imposed
in the future.
support "int imm8" instructions2020-01-16T07:51:17Ziximeowme@iximeow.net2020-01-16T07:51:17Zurn:sha1:f2de087952ce4bc10ba18ad6bbb5d34ff01d2921