just report it having one operand...

also adjust changelog for a 1.2.1 version again, no new interfaces to go
with these bugfixes.

registers `al`, `cl`, `dl`, and `bl` could have two different
representations - with `rex.w` and without. these two forms of `RegSpec`
would not compare equal, nor has the same, so for code relying on
`RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these
synonyms would introduce bugs in register analysis.

for example, in `yaxpeax-core`, this would result in instructions
writing to `rex.w al` not being visible as definitions for a future
read of `!rex.w al`.

fix this in `x86_64` code, add new test cases about the confusion,
adjust register names to make this situation more clearly a bug, and
introduce two new fuzz targets that would have helped spot this error.

* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be
  constructed in two ways that produce "identical" `RegSpec` that are..
  not.
  e.g. `RegSpec::al() != Regspec::rb(0)` even though
  `RegSpec::al().name() == RegSpec::rb(0).name()`.

  this corrects the `rb` constructor at least, but instructions like
  `4830c0` and `30c0` still produce incompatible versions of `al`.

* also fix register numbering used explicit qword-sized RegSpec
  constructors, r12 and r13 used to produce r8 and r9

these functions had a copypaste error where the r12 and r13 versions
would create RegSpec for registers 8 and 9 instead of 12 and 13. use
correct register numbers in these macros.