yaxpeax-x86/test/long_mode, branch 1.2.0

fix handling of lar/lsl source register

2023-07-24T13:41:02+00:00

fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}

2023-07-23T20:13:44+00:00

fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)

2023-07-23T18:06:55+00:00

annotation ordering changed a bit in refactoring, for the better???

2023-07-08T18:05:28+00:00

fix v(p)gather situations, get vex tests passing again

2023-07-08T18:04:55+00:00

fix operand handling for the psl/psr family of xmm shifts/rotates

2023-07-05T08:11:00+00:00

these instructions ignored rex bits even for xmm reigsters, which is
incorrect (so says xed)

two more test cases

2023-07-05T02:01:38+00:00

fix some dancing between bank size and RegisterBank enum values

2023-07-05T02:01:38+00:00

in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs
(respected rex.b when rex.b should have been ignored)

this seems to maybe improve runtime ever so slightly, but this is really
meant as a cleanup commit more than anything.

add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpers

2023-03-05T16:36:41+00:00

this request/suggestion comes from
[github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you!

pshufb annotations use incorrect register banks (for now?)

2022-05-30T16:32:43+00:00

the correct bank is applied far after register numbers are read. a
correct annotation would need to know to defer emission until setting
register banks, but also would need to work backwards for the number of
bits between the current byte and modrm. not impossible, but substantial
refactoring.