yaxpeax-x86/test/protected_mode, branch inst-behavior

3dnow was still supported on K8, K10. 32-bit mode should learn about uarch tweaks too

2025-06-01T23:51:42+00:00

expand isa feature selection to more bits

2025-06-01T09:21:37+00:00

this is backed by the new IsaSettings trait. the existing InstDecoders
are unchanged, except that they implement this new trait.

also add new `DecodeEverything` structs with `IsaSettings` impls that
are unconditionally set to permit anything the decoder can be configured
to conditionally accept or reject.

in the process, add new `_3dnow` flag and stop accepting 3dnow
instructions in uarch-specific decoder settings that would not have
3dnow instructions.

update AMD microarchitectures and cross-ref chip directory

rename most operand variants, make them structy rather than tupley

2024-06-24T19:48:45+00:00

add additional `call` test cases

2024-06-23T22:15:50+00:00

fix 32-bit 66-prefixed ff /2 call not having 16-bit operands

fix momentary regression in rendering `call` instructions to string

fix hreset being disassembled as having second operand of "Nothing"

2023-12-17T00:12:25+00:00

just report it having one operand...

fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set

2023-12-16T23:24:26+00:00

fix incorrect register selection for `vpmov*2m` with `rex.r` set

2023-12-16T23:05:08+00:00

fix incorrect register selection for `vpmovm2*` with `rex.b` set

2023-12-16T22:47:02+00:00

abnormal memory sizes for keylocker instructions are not bugs

2023-12-16T22:44:07+00:00

new `does_not_decode_invalid_registers` fuzzer found other bugs! the
384-bit accesses for 128b keylocker instructions are an
otherwise-unknown size and had a memory size of `BUG`. they are not
bugs. give the memory size a real name.

more RegSpec constructor validation, fix bug in x86_64 1b reg specs

2023-12-16T01:26:59+00:00

* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be
  constructed in two ways that produce "identical" `RegSpec` that are..
  not.
  e.g. `RegSpec::al() != Regspec::rb(0)` even though
  `RegSpec::al().name() == RegSpec::rb(0).name()`.

  this corrects the `rb` constructor at least, but instructions like
  `4830c0` and `30c0` still produce incompatible versions of `al`.

* also fix register numbering used explicit qword-sized RegSpec
  constructors, r12 and r13 used to produce r8 and r9