From 9827904a6aa6b649665cf78fa56716011fb37e6d Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 2 Mar 2015 15:34:34 -0800
Subject: initial commit

---
 src/msp430_instruction.2 | 100 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 src/msp430_instruction.2

(limited to 'src/msp430_instruction.2')

diff --git a/src/msp430_instruction.2 b/src/msp430_instruction.2
new file mode 100644
index 0000000..ccf1554
--- /dev/null
+++ b/src/msp430_instruction.2
@@ -0,0 +1,100 @@
+byteOpFlag: bit{1}
+
+RRC := b000
+SWPB:= b001
+RRA := b010
+SXT := b011
+PUSH:= b100
+CALL:= b101
+RETI:= b110
+
+oneOpCode: bit{3} :=
+  RRC | SWPB | RRA | SXT | PUSH | CALL | RETI
+
+JNE := b000
+JEQ := b001
+JNC := b010
+JC  := b011
+JN  := b100
+JGE := b101
+JL  := b110
+JMP := b111
+
+jumpCondition: bit{3} :=
+  JNE | JEQ | JNC | JC | JN | JGE | JL | JMP
+
+MOV := b0100
+ADD := b0101
+ADDC:= b0110
+SUBC:= b0111
+SUB := b1000
+CMP := b1001
+DADD:= b1010
+BIT := b1011
+BIC := b1100
+BIS := b1101
+XOR := b1110
+AND := b1111
+
+twoOpCode: bit{4} :=
+  MOV | ADD | ADDC | SUBC | SUB | CMP | DADD | BIT | BIC | BIS | XOR | AND
+
+Symbolic := b1
+Absolute := b1
+RegisterDirect := b0
+Indexed := b1
+
+twoOpDestMode: bit{1} :=
+  RegisterDirect | Indexed | Absolute | Symbolic
+
+NextWord := b11
+Const0 := b00
+Const1 := b01
+Const2 := b10
+Const4 := b10
+Const8 := b11
+ConstNeg1 := b11
+RegisterDirect := b00
+Indexed := b01
+RegisterIndirect := b10
+IndirectAutoInc := b11
+
+twoOpSourceMode: bit{2} :=
+  NextWord | Const0 | Const1 |
+  Const2 | Const4 | Const8 |
+  ConstNeg1 | RegisterDirect | Indexed |
+  RegisterIndirect | IndirectAutoInc
+
+oneOpDestMode: bit{2} := twoOpSourceMode
+
+twoOpDestModePrime :=
+  Symbolic:b0000 |
+  Absolute:b0010 |
+  RegisterDirect:register |
+  Indexed:register
+
+# replace with register names!
+twoOpSourceModePrime :=
+  NextWord:b0000
+  Const4:b0010
+  Const8:b0010
+  Const0:b0011
+  Const1:b0011
+  Const2:b0011
+  ConstNeg1:b0011
+  RegisterDirect:register
+  Indexed:register
+  RegisterIndirect:register
+  IndirectAutoInc:register
+
+sourceReg: bit{4}
+destReg: bit{4} := sourceReg
+
+noOp := b001:jumpCondition:pcOffset
+oneOp:= b000100:oneOpCode:byteOpFlag:oneOpDestMode:destReg
+twoOp := twoOpCode:sourceReg:twoOpDestMode:byteOpFlag:twoOpSourceMode:destReg
+twoOpRewrite $= twoOp =>
+  twoOpCode:byteOpFlag:twoOpSourceMode:sourceReg:sourceReg:twoOpDestMode:destReg:destReg
+twoOpPrime := twoOpCode:byteOpFlag:twoOpSourceModePrime:sourceReg:twoOpDestModePrime:destReg
+
+root := oneOp | twoOp | noOp
-- 
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