From 080d5513d90e6c2341316481fc7274f34666e658 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 30 Oct 2021 18:35:18 -0700 Subject: support ldp/stp/others, preindex writeback is optional --- src/armv8/a64.rs | 338 +++++++++++++++++++++++++++++++++++++++++++++--------- test/armv8/a64.rs | 88 +++++++------- 2 files changed, 329 insertions(+), 97 deletions(-) diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index d46c46e..e3e906f 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -1244,9 +1244,10 @@ pub enum Operand { ImmShift(u16, u8), RegShift(ShiftStyle, u8, SizeCode, u16), RegOffset(u16, i16), - RegRegOffset(u16, SizeCode, u16, ShiftStyle, u8), - RegPreIndex(u16, i16), - RegPostIndex(u16, i16), + RegRegOffset(u16, SizeCode, u16, SizeCode, ShiftStyle, u8), + RegPreIndex(u16, i32, bool), + RegPostIndex(u16, i32), + RegPostIndexReg(u16, u16), } impl Display for Operand { @@ -1421,33 +1422,27 @@ impl Display for Operand { write!(fmt, "[{}]", Operand::RegisterOrSP(SizeCode::X, *reg)) } } - Operand::RegRegOffset(reg, size_code, index_reg, extend, amount) => { - match size_code { - SizeCode::X => { - if *extend == ShiftStyle::LSL && *amount == 0 { - write!(fmt, "[x{}, x{}]", reg, index_reg) - } else { - write!(fmt, "[x{}, x{}, {} {}]", reg, index_reg, extend, amount) - } - }, - SizeCode::W => { - if *extend == ShiftStyle::LSL && *amount == 0 { - write!(fmt, "[x{}, w{}]", reg, index_reg) - } else { - write!(fmt, "[x{}, w{}, {} {}]", reg, index_reg, extend, amount) - } - } + Operand::RegRegOffset(reg, size_code, index_reg, index_size, extend, amount) => { + if *extend == ShiftStyle::LSL && *amount == 0 { + write!(fmt, "[{}, {}]", Operand::RegisterOrSP(*size_code, *reg), Operand::RegisterOrSP(*index_size, *index_reg)) + } else { + write!(fmt, "[{}, {}, {} {}]", Operand::RegisterOrSP(*size_code, *reg), Operand::RegisterOrSP(*index_size, *index_reg), extend, amount) } } - Operand::RegPreIndex(reg, offset) => { + Operand::RegPreIndex(reg, offset, wback) => { + let wback = if *wback { + "!" + } else { + "" + }; if *offset != 0 { if *offset < 0 { - write!(fmt, "[{}, -{:#x}]!", Operand::RegisterOrSP(SizeCode::X, *reg), -*offset) + write!(fmt, "[{}, -{:#x}]{}", Operand::RegisterOrSP(SizeCode::X, *reg), -*offset, wback) } else { - write!(fmt, "[{}, {:#x}]!", Operand::RegisterOrSP(SizeCode::X, *reg), offset) + write!(fmt, "[{}, {:#x}]{}", Operand::RegisterOrSP(SizeCode::X, *reg), offset, wback) } } else { - write!(fmt, "[{}]!", Operand::RegisterOrSP(SizeCode::X, *reg)) + write!(fmt, "[{}]{}", Operand::RegisterOrSP(SizeCode::X, *reg), wback) } } Operand::RegPostIndex(reg, offset) => { @@ -1461,6 +1456,9 @@ impl Display for Operand { write!(fmt, "[{}]", Operand::RegisterOrSP(SizeCode::X, *reg)) } } + Operand::RegPostIndexReg(reg, offset_reg) => { + write!(fmt, "[{}], x{}", Operand::RegisterOrSP(SizeCode::X, *reg), offset_reg) + } } } } @@ -2702,7 +2700,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), Operand::Register(size, Rt2), - Operand::RegPreIndex(Rn, imm7), + Operand::RegPreIndex(Rn, imm7 as i32, true), Operand::Nothing, ]; }, @@ -2733,7 +2731,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::SIMDRegister(size, Rt), Operand::SIMDRegister(size, Rt2), - Operand::RegPreIndex(Rn, imm7), + Operand::RegPreIndex(Rn, imm7 as i32, true), Operand::Nothing, ]; }, @@ -2785,7 +2783,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), Operand::Register(size, Rt2), - Operand::RegPostIndex(Rn, imm7), + Operand::RegPostIndex(Rn, imm7 as i32), Operand::Nothing ]; }, @@ -2794,7 +2792,55 @@ impl Decoder for InstDecoder { // V == 1 // let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); // eprintln!("C3.3.15 V==1, opc_L: {}", opc_L); - return Err(DecodeError::IncompleteDecoder); + let Rt = (word & 0x1f) as u16; + let Rn = ((word >> 5) & 0x1f) as u16; + let Rt2 = ((word >> 10) & 0x1f) as u16; + let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9; + let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); + let size = match opc_L { + 0b000 => { + inst.opcode = Opcode::STP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b001 => { + inst.opcode = Opcode::LDP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b010 => { + inst.opcode = Opcode::STP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b011 => { + inst.opcode = Opcode::LDP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b100 => { + inst.opcode = Opcode::STP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b101 => { + inst.opcode = Opcode::LDP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b110 | + 0b111 => { + inst.opcode = Opcode::Invalid; + SIMDSizeCode::Q + } + _ => { unreachable!("opc and L are three bits"); } + }; + inst.operands = [ + Operand::SIMDRegister(size, Rt), + Operand::SIMDRegister(size, Rt2), + Operand::RegPostIndex(Rn, imm7 as i32), + Operand::Nothing + ]; }, 0b10010 => { // load/store register pair (offset) @@ -2853,7 +2899,55 @@ impl Decoder for InstDecoder { // V == 1 // let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); // eprintln!("C3.3.14 V==1, opc_L: {}", opc_L); - return Err(DecodeError::IncompleteDecoder); + let Rt = (word & 0x1f) as u16; + let Rn = ((word >> 5) & 0x1f) as u16; + let Rt2 = ((word >> 10) & 0x1f) as u16; + let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9; + let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); + let size = match opc_L { + 0b000 => { + inst.opcode = Opcode::STP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b001 => { + inst.opcode = Opcode::LDP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b010 => { + inst.opcode = Opcode::STP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b011 => { + inst.opcode = Opcode::LDP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b100 => { + inst.opcode = Opcode::STP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b101 => { + inst.opcode = Opcode::LDP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b110 | + 0b111 => { + inst.opcode = Opcode::Invalid; + SIMDSizeCode::Q + } + _ => { unreachable!("opc and L are three bits"); } + }; + inst.operands = [ + Operand::SIMDRegister(size, Rt), + Operand::SIMDRegister(size, Rt2), + Operand::RegPreIndex(Rn, imm7 as i32, false), + Operand::Nothing + ]; }, 0b10011 => { // load/store register pair (pre-indexed) @@ -2903,7 +2997,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), Operand::Register(size, Rt2), - Operand::RegPreIndex(Rn, imm7), + Operand::RegPreIndex(Rn, imm7 as i32, true), Operand::Nothing ]; }, @@ -2912,7 +3006,55 @@ impl Decoder for InstDecoder { // V == 1 // let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); // eprintln!("C3.3.16 V==1, opc_L: {}", opc_L); - return Err(DecodeError::IncompleteDecoder); + let Rt = (word & 0x1f) as u16; + let Rn = ((word >> 5) & 0x1f) as u16; + let Rt2 = ((word >> 10) & 0x1f) as u16; + let mut imm7 = ((((word >> 15) & 0x7f) as i16) << 9) >> 9; + let opc_L = ((word >> 22) & 1) | ((word >> 29) & 0x6); + let size = match opc_L { + 0b000 => { + inst.opcode = Opcode::STP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b001 => { + inst.opcode = Opcode::LDP; + imm7 <<= 2; + SIMDSizeCode::S + }, + 0b010 => { + inst.opcode = Opcode::STP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b011 => { + inst.opcode = Opcode::LDP; + imm7 <<= 3; + SIMDSizeCode::D + }, + 0b100 => { + inst.opcode = Opcode::STP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b101 => { + inst.opcode = Opcode::LDP; + imm7 <<= 4; + SIMDSizeCode::Q + }, + 0b110 | + 0b111 => { + inst.opcode = Opcode::Invalid; + SIMDSizeCode::Q + } + _ => { unreachable!("opc and L are three bits"); } + }; + inst.operands = [ + Operand::SIMDRegister(size, Rt), + Operand::SIMDRegister(size, Rt2), + Operand::RegPreIndex(Rn, imm7 as i32, true), + Operand::Nothing + ]; }, 0b11000 | 0b11001 => { @@ -2994,7 +3136,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), - Operand::RegRegOffset(Rn, index_size, Rm, shift_style, S * shamt), + Operand::RegRegOffset(Rn, index_size, Rm, index_size, shift_style, S * shamt), Operand::Nothing, Operand::Nothing, ]; @@ -3063,7 +3205,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), - Operand::RegPreIndex(Rn, imm9), + Operand::RegPreIndex(Rn, imm9 as i32, true), Operand::Nothing, Operand::Nothing, ]; @@ -3095,9 +3237,9 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::Register(size, Rt), if category == 0b01 { - Operand::RegPostIndex(Rn, imm9) + Operand::RegPostIndex(Rn, imm9 as i32) } else { - Operand::RegPreIndex(Rn, imm9) + Operand::RegPreIndex(Rn, imm9 as i32, true) }, Operand::Nothing, Operand::Nothing, @@ -3159,7 +3301,7 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::SIMDRegister(size, Rt), - Operand::RegPreIndex(Rn, imm9), + Operand::RegPreIndex(Rn, imm9 as i32, false), Operand::Nothing, Operand::Nothing, ]; @@ -3208,9 +3350,9 @@ impl Decoder for InstDecoder { inst.operands = [ Operand::SIMDRegister(size, Rt), if pre_or_post == 1 { - Operand::RegPreIndex(Rn, imm9) + Operand::RegPreIndex(Rn, imm9 as i32, true) } else { - Operand::RegPostIndex(Rn, imm9) + Operand::RegPostIndex(Rn, imm9 as i32) }, Operand::Nothing, Operand::Nothing, @@ -3231,34 +3373,72 @@ impl Decoder for InstDecoder { 0b10 => { // Load/store register (register offset) // V == 1 - const OPCODES: &[Result] = &[ - Ok(Opcode::STR), - Ok(Opcode::LDR), - Ok(Opcode::STR), - Ok(Opcode::LDR), - Ok(Opcode::STR), - Ok(Opcode::LDR), - Ok(Opcode::STR), - Ok(Opcode::LDR), + const OPCODES: &[Result<(Opcode, SIMDSizeCode), DecodeError>] = &[ + // 00 1 00 + Ok((Opcode::STR, SIMDSizeCode::B)), + // 00 1 01 + Ok((Opcode::LDR, SIMDSizeCode::B)), + // 00 1 10 + Ok((Opcode::STR, SIMDSizeCode::Q)), + // 00 1 11 + Ok((Opcode::LDR, SIMDSizeCode::Q)), + // 01 1 00 + Ok((Opcode::STR, SIMDSizeCode::H)), + Ok((Opcode::LDR, SIMDSizeCode::H)), // 01 1 1x Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), // 10 1 0x - Ok(Opcode::STR), - Ok(Opcode::LDR), + Ok((Opcode::STR, SIMDSizeCode::S)), + Ok((Opcode::LDR, SIMDSizeCode::S)), // 10 1 1x Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), // 11 1 0x - Ok(Opcode::STR), - Ok(Opcode::LDR), + Ok((Opcode::STR, SIMDSizeCode::D)), + Ok((Opcode::LDR, SIMDSizeCode::D)), // 11 1 1x Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), ]; - inst.opcode = OPCODES[size_opc as usize]?; - return Err(DecodeError::IncompleteDecoder); + let size_bits = (word >> 30) & 0x03; + let option = (word >> 13) & 0x07; + let Rt = word & 0x1f; + let Rn = (word >> 5) & 0x1f; + let Rm = (word >> 16) & 0x1f; + let S = (word >> 12) & 0x01; + + let (opcode, size) = OPCODES[size_opc as usize]?; + let shift_amount = match size { + SIMDSizeCode::B => 1, + SIMDSizeCode::H => 1, + SIMDSizeCode::S => 2, + SIMDSizeCode::D => 3, + SIMDSizeCode::Q => 4, + }; + + let extend = if size == SIMDSizeCode::B && option == 0b011 { + ShiftStyle::LSL + } else { + const SHIFT_TYPES: &[ShiftStyle] = &[ + ShiftStyle::UXTB, ShiftStyle::UXTH, ShiftStyle::UXTW, ShiftStyle::LSL, + ShiftStyle::SXTB, ShiftStyle::SXTH, ShiftStyle::SXTW, ShiftStyle::SXTX, + ]; + SHIFT_TYPES[option as usize] + }; + + inst.opcode = opcode; + inst.operands = [ + Operand::SIMDRegister(size, Rt as u16), + Operand::RegRegOffset(Rn as u16, SizeCode::X, Rm as u16, if option & 0x01 == 0 { + SizeCode::W + } else { + SizeCode::X + }, extend, if S != 0 { shift_amount } else { 0 }), + Operand::Nothing, + Operand::Nothing, + ]; } _ => { // Load/store register (pac) @@ -3408,7 +3588,59 @@ impl Decoder for InstDecoder { 0b11111 => { // load/store register (unsigned immediate) // V == 1 - return Err(DecodeError::IncompleteDecoder); + let Rt = word & 0x1f; + let Rn = (word >> 5) & 0x1f; + let imm12 = (word >> 10) & 0xfff; + let opc = (word >> 22) & 0x3; + + let size_opc = ((word >> 28) & 0x0c) | opc; + + const OPCODES: &[Result<(Opcode, SIMDSizeCode), DecodeError>] = &[ + // 00 1 00 + Ok((Opcode::STR, SIMDSizeCode::B)), + // 00 1 01 + Ok((Opcode::LDR, SIMDSizeCode::B)), + // 00 1 10 + Ok((Opcode::STR, SIMDSizeCode::Q)), + // 00 1 11 + Ok((Opcode::LDR, SIMDSizeCode::Q)), + // 01 1 00 + Ok((Opcode::STR, SIMDSizeCode::H)), + Ok((Opcode::LDR, SIMDSizeCode::H)), + // 01 1 1x + Err(DecodeError::InvalidOpcode), + Err(DecodeError::InvalidOpcode), + // 10 1 0x + Ok((Opcode::STR, SIMDSizeCode::S)), + Ok((Opcode::LDR, SIMDSizeCode::S)), + // 10 1 1x + Err(DecodeError::InvalidOpcode), + Err(DecodeError::InvalidOpcode), + // 11 1 0x + Ok((Opcode::STR, SIMDSizeCode::D)), + Ok((Opcode::LDR, SIMDSizeCode::D)), + // 11 1 1x + Err(DecodeError::InvalidOpcode), + Err(DecodeError::InvalidOpcode), + ]; + + let (opc, size) = OPCODES[size_opc as usize]?; + + let offset_scale = match size { + SIMDSizeCode::B => 1, + SIMDSizeCode::H => 2, + SIMDSizeCode::S => 4, + SIMDSizeCode::D => 8, + SIMDSizeCode::Q => 16, + }; + + inst.opcode = opc; + inst.operands = [ + Operand::SIMDRegister(size, Rt as u16), + Operand::RegPreIndex(Rn as u16, (imm12 as u32 * offset_scale) as i32, false), + Operand::Nothing, + Operand::Nothing, + ]; }, 0b00100 => { // AdvSIMD load/store multiple structures diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs index 8de1f99..4d2815a 100644 --- a/test/armv8/a64.rs +++ b/test/armv8/a64.rs @@ -110,7 +110,7 @@ fn test_decode_str_ldr() { operands: [ Operand::Register(SizeCode::X, 29), Operand::Register(SizeCode::X, 30), - Operand::RegPreIndex(31, -0x20), + Operand::RegPreIndex(31, -0x20, true), Operand::Nothing, ] } @@ -2839,11 +2839,11 @@ fn test_openblas_simd_loadstore() { ([0x20, 0x04, 0xc1, 0x3c], "ldr q0, [x1], 0x10"), ([0x04, 0x06, 0xc1, 0x3c], "ldr q4, [x16], 0x10"), ([0x05, 0x06, 0xc1, 0x3c], "ldr q5, [x16], 0x10"), - ([0x34, 0x00, 0xc2, 0x3c], "ldur q20, [x1, 32]"), - ([0x3c, 0x00, 0xc6, 0x3c], "ldur q28, [x1, 96]"), - ([0x06, 0x02, 0xc6, 0x3c], "ldur q6, [x16, 96]"), - ([0x3e, 0x00, 0xc7, 0x3c], "ldur q30, [x1, 112]"), - ([0x07, 0x02, 0xc7, 0x3c], "ldur q7, [x16, 112]"), + ([0x34, 0x00, 0xc2, 0x3c], "ldur q20, [x1, 0x20]"), + ([0x3c, 0x00, 0xc6, 0x3c], "ldur q28, [x1, 0x60]"), + ([0x06, 0x02, 0xc6, 0x3c], "ldur q6, [x16, 0x60]"), + ([0x3e, 0x00, 0xc7, 0x3c], "ldur q30, [x1, 0x70]"), + ([0x07, 0x02, 0xc7, 0x3c], "ldur q7, [x16, 0x70]"), ([0x44, 0x00, 0xdf, 0x3c], "ldur q4, [x2, -0x10]"), ([0x60, 0x00, 0x80, 0x3d], "str q0, [x3]"), ([0x61, 0x00, 0x80, 0x3d], "str q1, [x3]"), @@ -2855,14 +2855,14 @@ fn test_openblas_simd_loadstore() { ([0xe0, 0x01, 0x80, 0x3d], "str q0, [x15]"), ([0xe3, 0x01, 0x80, 0x3d], "str q3, [x15]"), ([0x00, 0x02, 0x80, 0x3d], "str q0, [x16]"), - ([0xe0, 0x27, 0x80, 0x3d], "str q0, [sp, 144]"), - ([0xe1, 0x2b, 0x80, 0x3d], "str q1, [sp, 160]"), - ([0xe2, 0x2f, 0x80, 0x3d], "str q2, [sp, 176]"), - ([0xe3, 0x33, 0x80, 0x3d], "str q3, [sp, 192]"), - ([0xe4, 0x37, 0x80, 0x3d], "str q4, [sp, 208]"), - ([0xe5, 0x3b, 0x80, 0x3d], "str q5, [sp, 224]"), - ([0xe6, 0x3f, 0x80, 0x3d], "str q6, [sp, 240]"), - ([0xe7, 0x43, 0x80, 0x3d], "str q7, [sp, 256]"), + ([0xe0, 0x27, 0x80, 0x3d], "str q0, [sp, 0x90]"), + ([0xe1, 0x2b, 0x80, 0x3d], "str q1, [sp, 0xa0]"), + ([0xe2, 0x2f, 0x80, 0x3d], "str q2, [sp, 0xb0]"), + ([0xe3, 0x33, 0x80, 0x3d], "str q3, [sp, 0xc0]"), + ([0xe4, 0x37, 0x80, 0x3d], "str q4, [sp, 0xd0]"), + ([0xe5, 0x3b, 0x80, 0x3d], "str q5, [sp, 0xe0]"), + ([0xe6, 0x3f, 0x80, 0x3d], "str q6, [sp, 0xf0]"), + ([0xe7, 0x43, 0x80, 0x3d], "str q7, [sp, 0x100]"), ([0x20, 0x00, 0xc0, 0x3d], "ldr q0, [x1]"), ([0x21, 0x00, 0xc0, 0x3d], "ldr q1, [x1]"), ([0x24, 0x00, 0xc0, 0x3d], "ldr q4, [x1]"), @@ -2878,33 +2878,33 @@ fn test_openblas_simd_loadstore() { ([0x44, 0x01, 0xc0, 0x3d], "ldr q4, [x10]"), ([0xc1, 0x05, 0xc0, 0x3d], "ldr q1, [x14, 0x10]"), ([0xe5, 0x05, 0xc0, 0x3d], "ldr q5, [x15, 0x10]"), - ([0xc2, 0x09, 0xc0, 0x3d], "ldr q2, [x14, 32]"), - ([0xe6, 0x09, 0xc0, 0x3d], "ldr q6, [x15, 32]"), + ([0xc2, 0x09, 0xc0, 0x3d], "ldr q2, [x14, 0x20]"), + ([0xe6, 0x09, 0xc0, 0x3d], "ldr q6, [x15, 0x20]"), ([0x33, 0x0c, 0xc0, 0x3d], "ldr q19, [x1, 0x30]"), ([0x85, 0x0c, 0xc0, 0x3d], "ldr q5, [x4, 0x30]"), ([0x83, 0x0d, 0xc0, 0x3d], "ldr q3, [x12, 0x30]"), ([0xa7, 0x0d, 0xc0, 0x3d], "ldr q7, [x13, 0x30]"), ([0xc3, 0x0d, 0xc0, 0x3d], "ldr q3, [x14, 0x30]"), ([0xe7, 0x0d, 0xc0, 0x3d], "ldr q7, [x15, 0x30]"), - ([0x00, 0x06, 0xc1, 0xac], "ldp q0, q1, [x16], 32"), - ([0xbe, 0x7d, 0xc1, 0xac], "ldp q30, q31, [x13], 32"), + ([0x00, 0x06, 0xc1, 0xac], "ldp q0, q1, [x16], 0x20"), + ([0xbe, 0x7d, 0xc1, 0xac], "ldp q30, q31, [x13], 0x20"), ([0xb0, 0x44, 0x00, 0xad], "stp q16, q17, [x5]"), - ([0x82, 0x0d, 0x01, 0xad], "stp q2, q3, [x12, 32]"), - ([0xc2, 0x0d, 0x01, 0xad], "stp q2, q3, [x14, 32]"), - ([0xb8, 0x64, 0x02, 0xad], "stp q24, q25, [x5, 64]"), - ([0xba, 0x6c, 0x03, 0xad], "stp q26, q27, [x5, 96]"), + ([0x82, 0x0d, 0x01, 0xad], "stp q2, q3, [x12, 0x20]"), + ([0xc2, 0x0d, 0x01, 0xad], "stp q2, q3, [x14, 0x20]"), + ([0xb8, 0x64, 0x02, 0xad], "stp q24, q25, [x5, 0x40]"), + ([0xba, 0x6c, 0x03, 0xad], "stp q26, q27, [x5, 0x60]"), ([0xc0, 0x04, 0x40, 0xad], "ldp q0, q1, [x6]"), ([0xb0, 0x44, 0x40, 0xad], "ldp q16, q17, [x5]"), - ([0x02, 0x0e, 0x41, 0xad], "ldp q2, q3, [x16, 32]"), - ([0x68, 0x25, 0x41, 0xad], "ldp q8, q9, [x11, 32]"), - ([0x6c, 0x35, 0x41, 0xad], "ldp q12, q13, [x11, 32]"), - ([0x7c, 0x74, 0x42, 0xad], "ldp q28, q29, [x3, 64]"), - ([0x02, 0x0e, 0x43, 0xad], "ldp q2, q3, [x16, 96]"), - ([0x06, 0x1e, 0x43, 0xad], "ldp q6, q7, [x16, 96]"), - ([0x30, 0x44, 0x43, 0xad], "ldp q16, q17, [x1, 96]"), - ([0x3e, 0x7c, 0x47, 0xad], "ldp q30, q31, [x1, 224]"), + ([0x02, 0x0e, 0x41, 0xad], "ldp q2, q3, [x16, 0x20]"), + ([0x68, 0x25, 0x41, 0xad], "ldp q8, q9, [x11, 0x20]"), + ([0x6c, 0x35, 0x41, 0xad], "ldp q12, q13, [x11, 0x20]"), + ([0x7c, 0x74, 0x42, 0xad], "ldp q28, q29, [x3, 0x40]"), + ([0x02, 0x0e, 0x43, 0xad], "ldp q2, q3, [x16, 0x60]"), + ([0x06, 0x1e, 0x43, 0xad], "ldp q6, q7, [x16, 0x60]"), + ([0x30, 0x44, 0x43, 0xad], "ldp q16, q17, [x1, 0x60]"), + ([0x3e, 0x7c, 0x47, 0xad], "ldp q30, q31, [x1, 0xe0]"), ([0x6e, 0x3d, 0xc1, 0x6c], "ldp d14, d15, [x11], 0x10"), - ([0xe8, 0x27, 0xc4, 0x6c], "ldp d8, d9, [sp], 64"), + ([0xe8, 0x27, 0xc4, 0x6c], "ldp d8, d9, [sp], 0x40"), ([0x81, 0x01, 0x00, 0x6d], "stp d1, d0, [x12]"), ([0x39, 0x60, 0x00, 0x6d], "stp d25, d24, [x1]"), ([0xdd, 0x71, 0x01, 0x6d], "stp d29, d28, [x14, 0x10]"), @@ -2937,13 +2937,13 @@ fn test_openblas_simd_loadstore() { ([0x22, 0x6b, 0x78, 0xfc], "ldr d2, [x25, x24]"), ([0x08, 0x78, 0x78, 0xfc], "ldr d8, [x0, x24, lsl 3]"), ([0xf3, 0x9b, 0x41, 0xfd], "ldr d19, [sp, 0x330]"), - ([0x4a, 0x44, 0x47, 0xfd], "ldr d10, [x2, 3720]"), - ([0x01, 0xd0, 0x47, 0xfd], "ldr d1, [x0, 4000]"), + ([0x4a, 0x44, 0x47, 0xfd], "ldr d10, [x2, 0xe88]"), + ([0x01, 0xd0, 0x47, 0xfd], "ldr d1, [x0, 0xfa0]"), ([0xe8, 0x27, 0xbc, 0x6d], "stp d8, d9, [sp, -0x40]!"), ([0xe8, 0x27, 0xbf, 0x6d], "stp d8, d9, [sp, -0x10]!"), - ([0xa2, 0x0f, 0x32, 0x3d], "str b2, [x29, 3203]"), - ([0x97, 0xff, 0xff, 0x1c], "ldr s23, 8b95f8 "), - ([0x6e, 0x3d, 0xc1, 0x2c], "ldp s14, s15, [x11], 8"), + ([0xa2, 0x0f, 0x32, 0x3d], "str b2, [x29, 0xc83]"), + ([0x97, 0xff, 0xff, 0x1c], "ldr s23, $-0x10"), + ([0x6e, 0x3d, 0xc1, 0x2c], "ldp s14, s15, [x11], 0x8"), ([0xef, 0x7e, 0x40, 0x2d], "ldp s15, s31, [x23]"), ([0x41, 0x80, 0x40, 0x2d], "ldp s1, s0, [x2, 0x4]"), ([0x33, 0xd0, 0x7f, 0x2d], "ldp s19, s20, [x1, -0x4]"), @@ -2964,8 +2964,8 @@ fn test_openblas_simd_loadstore() { ([0x88, 0x7b, 0x21, 0xbc], "str s8, [x28, x1, lsl 2]"), ([0x60, 0xda, 0x21, 0xbc], "str s0, [x19, w1, sxtw 2]"), ([0xc0, 0x5a, 0x32, 0xbc], "str s0, [x22, w18, uxtw 2]"), - ([0xb3, 0x85, 0x40, 0xbc], "ldr s19, [x13], 8"), - ([0x02, 0x8f, 0x40, 0xbc], "ldr s2, [x24, 8]!"), + ([0xb3, 0x85, 0x40, 0xbc], "ldr s19, [x13], 0x8"), + ([0x02, 0x8f, 0x40, 0xbc], "ldr s2, [x24, 0x8]!"), ([0x71, 0x05, 0x41, 0xbc], "ldr s17, [x11], 0x10"), ([0xe0, 0x42, 0x5d, 0xbc], "ldur s0, [x23, -0x2c]"), ([0x27, 0x80, 0x5d, 0xbc], "ldur s7, [x1, -0x28]"), @@ -2980,10 +2980,10 @@ fn test_openblas_simd_loadstore() { ([0x49, 0x03, 0x00, 0xbd], "str s9, [x26]"), ([0x62, 0x78, 0x00, 0xbd], "str s2, [x3, 0x78]"), ([0x6c, 0x78, 0x00, 0xbd], "str s12, [x3, 0x78]"), - ([0xea, 0x7f, 0x00, 0xbd], "str s10, [sp, 124]"), - ([0xe9, 0x87, 0x04, 0xbd], "str s9, [sp, 1156]"), - ([0xc0, 0x8a, 0x0a, 0xbd], "str s0, [x22, 2696]"), - ([0x41, 0x58, 0x4f, 0xbd], "ldr s1, [x2, 3928]"), + ([0xea, 0x7f, 0x00, 0xbd], "str s10, [sp, 0x7c]"), + ([0xe9, 0x87, 0x04, 0xbd], "str s9, [sp, 0x484]"), + ([0xc0, 0x8a, 0x0a, 0xbd], "str s0, [x22, 0xa88]"), + ([0x41, 0x58, 0x4f, 0xbd], "ldr s1, [x2, 0xf58]"), ([0x88, 0x7c, 0x00, 0x2d], "stp s8, s31, [x4]"), ([0x03, 0x84, 0x00, 0x2d], "stp s3, s1, [x0, 0x4]"), ([0x13, 0xdc, 0x3f, 0x2d], "stp s19, s23, [x0, -0x4]"), @@ -4109,8 +4109,8 @@ fn test_openblas_simd_ops() { ([0x7b, 0x1f, 0x3b, 0x6e], "eor v27.16b, v27.16b, v27.16b"), ([0xbd, 0x1f, 0x3d, 0x6e], "eor v29.16b, v29.16b, v29.16b"), ([0xff, 0x1f, 0x3f, 0x6e], "eor v31.16b, v31.16b, v31.16b"), - ([0xa5, 0x40, 0x05, 0x6e], "ext v5.16b, v5.16b, v5.16b, 8"), - ([0xc7, 0x40, 0x06, 0x6e], "ext v7.16b, v6.16b, v6.16b, 8"), + ([0xa5, 0x40, 0x05, 0x6e], "ext v5.16b, v5.16b, v5.16b, 0x8"), + ([0xc7, 0x40, 0x06, 0x6e], "ext v7.16b, v6.16b, v6.16b, 0x8"), ([0x02, 0x1d, 0x21, 0x0e], "and v2.8b, v8.8b, v1.8b"), ([0x21, 0x1c, 0x22, 0x0e], "and v1.8b, v1.8b, v2.8b"), ([0x21, 0x1c, 0x32, 0x0e], "and v1.8b, v1.8b, v18.8b"), -- cgit v1.1