From 268f54ec676666467fdceda5e86d89ea27d211b8 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 5 Dec 2020 20:24:22 -0800 Subject: fix off by one in a mask for data-processing (shifted register) --- src/armv7/thumb.rs | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index 9595e1f..bf492df 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -128,10 +128,11 @@ pub fn decode_into>(decoder: &InstDecoder, inst: &mut I if opword < 0b11110 { // op1 == 0b01 + // interpret `op1 == 0b01` lines of table `A6-9` if !op2[6] { // `op2` is `0b00.. ` or `0b01..` if !op2[5] { - // `Load/store`, either `multiple` or `dual` + // `op2` is `00xxxxx`, and is `Load/store`, either `multiple` or `dual` let rn = instr2[..4].load::(); // TODO: double check if op2[2] { @@ -696,9 +697,10 @@ pub fn decode_into>(decoder: &InstDecoder, inst: &mut I } } } else { + // op2 is `01xxxxx` and is: // `Data-processing (shfited register)` (`A6-241`) // v6T2 - let op = op2[0..4].load::(); + let op = op2[1..5].load::(); let s = instr2[4]; let rn = instr2[0..4].load::(); let rd = lower2[8..12].load::(); @@ -1179,8 +1181,7 @@ pub fn decode_into>(decoder: &InstDecoder, inst: &mut I // v6T2 let op = instr2[4..9].load::(); let i = instr2[10..11].load::(); - let s = instr2[4]; - inst.s = s; + inst.s = false; let rn = instr2[0..4].load::(); let imm3 = lower2[12..15].load::(); let rd = lower2[8..12].load::(); @@ -1192,6 +1193,7 @@ pub fn decode_into>(decoder: &InstDecoder, inst: &mut I if rn != 0b1111 { // `ADD` (`A8-304`) // v6T2 + // encoding T4 inst.opcode = Opcode::ADD; inst.operands = [ Operand::Reg(Reg::from_u8(rd)), @@ -1226,6 +1228,7 @@ pub fn decode_into>(decoder: &InstDecoder, inst: &mut I if rn != 0b1111 { // `SUB` (`A8-709`) // v6T2 + // encoding T4 inst.opcode = Opcode::SUB; inst.operands = [ Operand::Reg(Reg::from_u8(rd)), -- cgit v1.1