From 4281309f580130c3642d50b79034f0428b662c55 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 2 Aug 2026 23:43:23 +0000 Subject: fix swapped rfe{ia,db} and srs{ia,db} --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 30b3866..c534c70 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,6 +16,7 @@ saved) program status register, was reported as a banked GPR. * thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*` * thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register) +* thumb2: rfeia and rfedb were decoded backwards. likewise for srsia and srsdb * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT` (formatted as any of `tt`, `ttt`, `tta`, `ttat`) * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions, -- cgit v1.1