From 9e9c7b2663fa52881bf6883e74f4cd8610c38570 Mon Sep 17 00:00:00 2001 From: Brandon Ros Date: Fri, 3 Jul 2026 00:14:45 -0400 Subject: fix more thumb2 register data-processing decode bugs - register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as lsl: the shift type was read from hw1[6:5] (always 0 for this form) instead of hw0[6:5] - 32-bit uxt*/sxt* extends read the ror amount from the wrong field (hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation extend came back as ror #4; rotation of 0 is now omitted - sxtab was decoded as sxtah (wrong opcode table entry) all cases verified against binutils objdump --- CHANGELOG | 3 +++ 1 file changed, 3 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 5a6dc75..5de5ee7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -28,6 +28,9 @@ as well as thumb2 fixes from @brandonros: * thumb2: some instructions had outright incorrect opcodes: * ror (immediate) was decoded as asr, * mvn (immediate) was decoded as mov, + * sxtab was decoded as sxtah, + * lsl, lsr, asr, ror were determining opcode from an incorrect bitfield, +* thumb2: (un)signed extend-and-rotate loaded an incorrect field for rotate, thank you for the patches! -- cgit v1.1