From bbbb546ee0b73d295be891b1b2e0e5a18cbfd3d1 Mon Sep 17 00:00:00 2001 From: Brandon Ros Date: Fri, 3 Jul 2026 20:48:35 -0400 Subject: fix thumb2 TBH decode: wrong opcode and register-shift operand the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 5de5ee7..c2cc889 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -30,6 +30,7 @@ as well as thumb2 fixes from @brandonros: * mvn (immediate) was decoded as mov, * sxtab was decoded as sxtah, * lsl, lsr, asr, ror were determining opcode from an incorrect bitfield, + * tbh was decoded as an shifted tbb, * thumb2: (un)signed extend-and-rotate loaded an incorrect field for rotate, thank you for the patches! -- cgit v1.1