From ecec44cbee7be32e632b24ae0e4fe3f84e6e8ef8 Mon Sep 17 00:00:00 2001 From: iximeow Date: Fri, 11 Sep 2026 16:08:55 +0000 Subject: fix issues around unpredictable ldrd and offset printing --- CHANGELOG | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 61e29c0..19dd69b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -27,6 +27,15 @@ rather than pc * thumb2: several instructions which decode an explicit rotate operand now do so into a distinct Operand::Ror (sxth, uxth, stxb16, utxb16, sxtb, uxtb) +* thumb2: have unpredictable ldrd (literal) match a more "typical" interpretation + when ldrd is encoded as post-index with writeback, the manual describes the + behavior as "unpredictable", but capstone and others report this as a + post-index as the bits imply. yaxpeax will still reject this encoding if + configured to reject unpredictable instructions. +* ARMv7: do not try to elide memory offset when 0 in postindex operands. + this makes a post-index (and implied writeback!) ambiguous with a pre-indexed + access with offset zero. that is, `[r1, 0]` may be written as `[r1]`, but + `[r1], 0` has a different meaning than `[r1]`. * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT` (formatted as any of `tt`, `ttt`, `tta`, `ttat`) * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions, -- cgit v1.1