From 06949d312514850645f3c2bcaa3e0cdc95a6c545 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 19 Oct 2025 23:06:14 +0000
Subject: Opcode and Operand should be non-exhaustive

but exhaustiveness checking is very valuable here, so allow it to be
disabled. caveats apply. read the docs in Cargo.toml.
---
 src/armv7.rs | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/armv7.rs')

diff --git a/src/armv7.rs b/src/armv7.rs
index b1ae2ba..3e289b6 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -39,6 +39,7 @@ pub struct NoContext;
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[allow(non_camel_case_types)]
 #[allow(missing_docs)]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
 pub enum Opcode {
     Invalid,
     /*
@@ -606,6 +607,7 @@ impl StatusRegMask {
 
 /// an operand in an `arm` instruction.
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
 pub enum Operand {
     /// a general-purpose register.
     Reg(Reg),
-- 
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