From a00a54539d9124d8b376ee9cbeab355d99c9d163 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Fri, 11 Sep 2026 15:57:22 +0000
Subject: fix {s,u}xt{h,b}[16] using an immediate to describe their rotates

---
 src/armv7.rs | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/armv7.rs')

diff --git a/src/armv7.rs b/src/armv7.rs
index 87b44f5..30a8960 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -775,6 +775,10 @@ pub enum Operand {
     BankedSPSR(Bank),
     /// a mask of bits for the `spsr` register.
     StatusRegMask(StatusRegMask),
+    /// a standalone rotate right by the specified amount.
+    ///
+    /// this typically applies equally to multiple operands; see `sxtah`, `uxtah`, etc.
+    Ror(u8),
     /// the `apsr` register.
     APSR,
     /// the `spsr` register.
@@ -846,6 +850,8 @@ pub trait OperandVisitor {
     fn visit_banked_spsr(&mut self, bank: Bank) -> Result<Self::Ok, Self::Error>;
     /// process an operand that is some set of bits out of a status register.
     fn visit_status_reg_mask(&mut self, mask: StatusRegMask) -> Result<Self::Ok, Self::Error>;
+    /// process an operand that is a standalone rotate of other operands in the instruction.
+    fn visit_rotate(&mut self, amt: u8) -> Result<Self::Ok, Self::Error>;
     /// process an operand that is `APSR`.
     fn visit_apsr(&mut self) -> Result<Self::Ok, Self::Error>;
     /// process an operand that is `SPSR`.
-- 
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