From bbbb546ee0b73d295be891b1b2e0e5a18cbfd3d1 Mon Sep 17 00:00:00 2001 From: Brandon Ros Date: Fri, 3 Jul 2026 20:48:35 -0400 Subject: fix thumb2 TBH decode: wrong opcode and register-shift operand the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. --- src/armv7/thumb.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/armv7/thumb.rs') diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index e9427d1..7aa3a5d 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -357,15 +357,14 @@ pub fn decode_into::Address, ::Word>>(d // TODO: should_is_must() // rt == 0b1111 // rd == 0b0000 - inst.opcode = Opcode::TBB; + inst.opcode = Opcode::TBH; inst.operands = [ Operand::RegDerefPreindexRegShift( Reg::from_u8(rn), // want `, LSL #1`, construct a raw shift - // ourselves + // ourselves. bit 4 clear selects `RegImm`. RegShift::from_raw( - 0b10000 | // `RegImm` - rd as u16 | // reg == rd + rd as u16 | // reg == rm (0b00 << 5) | // LSL (1 << 7) // shift == #1 ), -- cgit v1.1