From cf151c1dc6926bf7d14eb5a50afe42b79e6fd481 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Fri, 11 Sep 2026 16:12:12 +0000
Subject: fix ssat/16 second operand off by one, testcases

---
 src/armv7/thumb.rs | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'src/armv7')

diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs
index 077834a..dacf3dd 100644
--- a/src/armv7/thumb.rs
+++ b/src/armv7/thumb.rs
@@ -1452,7 +1452,8 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                             inst.opcode = Opcode::SSAT;
                             inst.operands = [
                                 Operand::Reg(Reg::from_u8(rd)),
-                                Operand::Imm32((lower & 0b11111) as u32),
+                                // TODO:  ssat r3, #0x3, r7, lsl #22 != ssat r3, #4, r7, lsl #0x16. bytes: [7, f3, 83, 53]
+                                Operand::Imm32((lower & 0b11111) as u32 + 1),
                                 Operand::RegShift(shift),
                                 Operand::Nothing,
                             ];
@@ -1466,7 +1467,8 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                                 inst.opcode = Opcode::SSAT;
                                 inst.operands = [
                                     Operand::Reg(Reg::from_u8(rd)),
-                                    Operand::Imm32((lower & 0b11111) as u32),
+                                // TODO:  ssat r3, #0x3, r7, lsl #22 != ssat r3, #4, r7, lsl #0x16. bytes: [7, f3, 83, 53]
+                                    Operand::Imm32((lower & 0b11111) as u32 + 1),
                                     Operand::RegShift(shift),
                                     Operand::Nothing,
                                 ];
@@ -1476,7 +1478,8 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                                 inst.opcode = Opcode::SSAT16;
                                 inst.operands = [
                                     Operand::Reg(Reg::from_u8(rd)),
-                                    Operand::Imm32((lower & 0b11111) as u32),
+                                    // TODO: testcase
+                                    Operand::Imm32((lower & 0b11111) as u32 + 1),
                                     Operand::Reg(Reg::from_u8(rn)),
                                     Operand::Nothing,
                                 ];
-- 
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