From 06949d312514850645f3c2bcaa3e0cdc95a6c545 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 19 Oct 2025 23:06:14 +0000
Subject: Opcode and Operand should be non-exhaustive

but exhaustiveness checking is very valuable here, so allow it to be
disabled. caveats apply. read the docs in Cargo.toml.
---
 src/armv8/a64.rs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/armv8')

diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index 140e616..075efc2 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -1147,7 +1147,7 @@ impl SysOps {
 #[derive(Copy, Clone, Debug, PartialEq)]
 #[repr(u16)]
 #[allow(missing_docs)]
-#[non_exhaustive]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
 pub enum Opcode {
     Invalid,
     UDF,
@@ -2795,6 +2795,7 @@ impl Display for ShiftStyle {
 /// in practice; no `aarch64` instruction has multiple `Operand::PCOffset` entries, for example.
 #[derive(Copy, Clone, Debug, PartialEq)]
 #[repr(C)]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
 pub enum Operand {
     /// "no operand". since an instruction's `operands` array is always four entries, this is used
     /// to fill space, if any, after recording an instruction's extant operands.
-- 
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