From b60eb569ebf1ea1769cfd8cd9e9a388cd8569bef Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Tue, 28 Dec 2021 20:12:08 -0800
Subject: handle a few more invalid instructions

---
 src/armv8/a64.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/armv8')

diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index a33bc7a..95458ca 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -8990,6 +8990,10 @@ impl Decoder<ARMv8> for InstDecoder {
                             Err(DecodeError::InvalidOpcode),
                             Ok((Opcode::ST1, 2)),
                             Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
                         ];
 
                         let (opcode, num_regs) = OPCODES[opcode_bits as usize]?;
@@ -9047,6 +9051,10 @@ impl Decoder<ARMv8> for InstDecoder {
                             Err(DecodeError::InvalidOpcode),
                             Ok((Opcode::ST1, 2)),
                             Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
+                            Err(DecodeError::InvalidOpcode),
                         ];
 
                         let (opcode, num_regs) = OPCODES[opcode_bits as usize]?;
-- 
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