From 9570dae514462f4a823e54de11e6dc86587de1b7 Mon Sep 17 00:00:00 2001
From: Mitchell Johnson <ehntoo@ehntoo.org>
Date: Sun, 4 Sep 2022 19:49:46 -0400
Subject: Fix 32-bit conditional thumb branches

Correct the shift used to select condition bits and correctly compute the
branch offset.
---
 src/armv7/thumb.rs | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs
index 2e960b1..45151cd 100644
--- a/src/armv7/thumb.rs
+++ b/src/armv7/thumb.rs
@@ -1491,10 +1491,22 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                     if op & 0b0111000 != 0b0111000 {
                         // `Conditional branch` (`A8-332`)
                         // v6T2
-                        inst.condition = ConditionCode::build(((instr >> 8) & 0b1111) as u8);
+                        let imm11 = lower2[0..11].load::<u32>();
+                        let imm6 = instr2[0..6].load::<u32>();
+                        let s = instr2[10..11].load::<u32>();
+                        let j1 = lower2[13..14].load::<u32>();
+                        let j2 = lower2[11..12].load::<u32>();
+                        let imm =
+                            (imm11 as i32) |
+                            ((imm6 as i32) << 11) |
+                            ((j1 as i32) << 17) |
+                            ((j2 as i32) << 18) |
+                            ((s as i32) << 19);
+                        let imm = (imm << 12) >> 12;
+                        inst.condition = ConditionCode::build(((instr >> 6) & 0b1111) as u8);
                         inst.opcode = Opcode::B;
                         inst.operands = [
-                            Operand::BranchThumbOffset(((instr & 0b11111111) + 1) as i8 as i32),
+                            Operand::BranchThumbOffset(imm),
                             Operand::Nothing,
                             Operand::Nothing,
                             Operand::Nothing,
-- 
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