From ac74d253a15616dbad0256e81bf32d02b492dcc3 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 25 Oct 2021 00:41:03 -0700
Subject: shifted/extended add/sub is contingent on bit 21, not 17

the comment was even correct! but the actual check was not.
---
 src/armv8/a64.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index b6365e6..fca9e15 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -1686,7 +1686,7 @@ impl Decoder<ARMv8> for InstDecoder {
                         let size = if sf { SizeCode::X } else { SizeCode::W };
 
                         // and operands are contingent on bit 21
-                        if (word & 0x20000) != 0 {
+                        if (word & 0x20_0000) != 0 {
                             // extended form
                             // opt (bits 22, 23) must be 0
 
-- 
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