From b077973907857abc777383acc9638830d7745a86 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 25 Oct 2021 19:55:07 -0700
Subject: madd/msub aliases

---
 src/armv8/a64.rs | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src')

diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs
index 52c90bc..b901d21 100644
--- a/src/armv8/a64.rs
+++ b/src/armv8/a64.rs
@@ -804,24 +804,42 @@ impl Display for Instruction {
                 write!(fmt, "cls")?;
             }
             Opcode::MADD => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "mul {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "madd")?;
             }
             Opcode::MSUB => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "mneg {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "msub")?;
             }
             Opcode::SMADDL => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "smull {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "smaddl")?;
             }
             Opcode::SMSUBL => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "smnegl {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "smsubl")?;
             }
             Opcode::SMULH => {
                 write!(fmt, "smulh")?;
             }
             Opcode::UMADDL => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "umull {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "umaddl")?;
             }
             Opcode::UMSUBL => {
+                if let Operand::Register(_, 31) = self.operands[3] {
+                    return write!(fmt, "umnegl {}, {}, {}", self.operands[0], self.operands[1], self.operands[2])
+                }
                 write!(fmt, "umsubl")?;
             }
             Opcode::UMULH => {
-- 
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