From b92bd2d1c03ec9a65a947b3bb6f24f4529905815 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sat, 30 Oct 2021 18:34:02 -0700
Subject: support simd load/store (single structure)

---
 test/armv8/a64.rs | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'test/armv8')

diff --git a/test/armv8/a64.rs b/test/armv8/a64.rs
index 69039e7..8de1f99 100644
--- a/test/armv8/a64.rs
+++ b/test/armv8/a64.rs
@@ -2749,9 +2749,9 @@ fn test_openblas_simd_loadstore() {
         ([0xa4, 0x89, 0x40, 0x0c], "ld2 {v4.2s, v5.2s}, [x13]"),
         ([0xa2, 0xa9, 0x40, 0x0c], "ld1 {v2.2s, v3.2s}, [x13]"),
         ([0xac, 0xa9, 0x40, 0x0c], "ld1 {v12.2s, v13.2s}, [x13]"),
-        ([0xa5, 0x79, 0x9f, 0x0c], "st1 {v5.2s}, [x13], 8"),
+        ([0xa5, 0x79, 0x9f, 0x0c], "st1 {v5.2s}, [x13], 0x8"),
         ([0x45, 0x79, 0xc2, 0x0c], "ld1 {v5.2s}, [x10], x2"),
-        ([0x20, 0x78, 0xdf, 0x0c], "ld1 {v0.2s}, [x1], 8"),
+        ([0x20, 0x78, 0xdf, 0x0c], "ld1 {v0.2s}, [x1], 0x8"),
         ([0xcc, 0x85, 0x00, 0x0d], "st1 {v12.d}[0], [x14]"),
         ([0xa8, 0x91, 0x00, 0x0d], "st1 {v8.s}[1], [x13]"),
         ([0xa0, 0x81, 0x20, 0x0d], "st2 {v0.s, v1.s}[0], [x13]"),
@@ -2762,7 +2762,7 @@ fn test_openblas_simd_loadstore() {
         ([0x64, 0x90, 0x9f, 0x0d], "st1 {v4.s}[1], [x3], 0x4"),
         ([0x22, 0x84, 0xc2, 0x0d], "ld1 {v2.d}[0], [x1], x2"),
         ([0x61, 0x80, 0xc4, 0x0d], "ld1 {v1.s}[0], [x3], x4"),
-        ([0x24, 0xc9, 0xdf, 0x0d], "ld1r {v4.2s}, [x9], 0x4"),
+        ([0x24, 0xc9, 0xdf, 0x0d], "ld1r {v4.2s}, [x9], 0x4"), // TODO: could use a test for "ld1r {v4.2s}, [x9]"
         ([0x88, 0x28, 0x00, 0x4c], "st1 {v8.4s-v11.4s}, [x4]"),
         ([0x60, 0x2d, 0x00, 0x4c], "st1 {v0.2d-v3.2d}, [x11]"),
         ([0x9c, 0x2e, 0x00, 0x4c], "st1 {v28.2d-v31.2d}, [x20]"),
@@ -2801,22 +2801,22 @@ fn test_openblas_simd_loadstore() {
         ([0xa4, 0x8d, 0x40, 0x4c], "ld2 {v4.2d, v5.2d}, [x13]"),
         ([0xa6, 0x8d, 0x40, 0x4c], "ld2 {v6.2d, v7.2d}, [x13]"),
         ([0xa3, 0x7c, 0x86, 0x4c], "st1 {v3.2d}, [x5], x6"),
-        ([0x61, 0x2c, 0x9f, 0x4c], "st1 {v1.2d-v4.2d}, [x3], 64"),
-        ([0xb0, 0x2c, 0x9f, 0x4c], "st1 {v16.2d-v19.2d}, [x5], 64"),
+        ([0x61, 0x2c, 0x9f, 0x4c], "st1 {v1.2d-v4.2d}, [x3], 0x40"),
+        ([0xb0, 0x2c, 0x9f, 0x4c], "st1 {v16.2d-v19.2d}, [x5], 0x40"),
         ([0x24, 0x78, 0x9f, 0x4c], "st1 {v4.4s}, [x1], 0x10"),
         ([0xa5, 0x7d, 0x9f, 0x4c], "st1 {v5.2d}, [x13], 0x10"),
-        ([0xa4, 0x88, 0x9f, 0x4c], "st2 {v4.4s, v5.4s}, [x5], 32"),
-        ([0xc4, 0x88, 0x9f, 0x4c], "st2 {v4.4s, v5.4s}, [x6], 32"),
-        ([0xb0, 0xad, 0x9f, 0x4c], "st1 {v16.2d, v17.2d}, [x13], 32"),
+        ([0xa4, 0x88, 0x9f, 0x4c], "st2 {v4.4s, v5.4s}, [x5], 0x20"),
+        ([0xc4, 0x88, 0x9f, 0x4c], "st2 {v4.4s, v5.4s}, [x6], 0x20"),
+        ([0xb0, 0xad, 0x9f, 0x4c], "st1 {v16.2d, v17.2d}, [x13], 0x20"),
         ([0x20, 0x7c, 0xc2, 0x4c], "ld1 {v0.2d}, [x1], x2"),
         ([0x46, 0x7d, 0xc6, 0x4c], "ld1 {v6.2d}, [x10], x6"),
-        ([0x20, 0x0c, 0xdf, 0x4c], "ld4 {v0.2d-v3.2d}, [x1], 64"),
-        ([0x51, 0x2d, 0xdf, 0x4c], "ld1 {v17.2d-v20.2d}, [x10], 64"),
+        ([0x20, 0x0c, 0xdf, 0x4c], "ld4 {v0.2d-v3.2d}, [x1], 0x40"),
+        ([0x51, 0x2d, 0xdf, 0x4c], "ld1 {v17.2d-v20.2d}, [x10], 0x40"),
         ([0x20, 0x78, 0xdf, 0x4c], "ld1 {v0.4s}, [x1], 0x10"),
         ([0x21, 0x78, 0xdf, 0x4c], "ld1 {v1.4s}, [x1], 0x10"),
         ([0x46, 0x7d, 0xdf, 0x4c], "ld1 {v6.2d}, [x10], 0x10"),
-        ([0x20, 0x88, 0xdf, 0x4c], "ld2 {v0.4s, v1.4s}, [x1], 32"),
-        ([0x50, 0xad, 0xdf, 0x4c], "ld1 {v16.2d, v17.2d}, [x10], 32"),
+        ([0x20, 0x88, 0xdf, 0x4c], "ld2 {v0.4s, v1.4s}, [x1], 0x20"),
+        ([0x50, 0xad, 0xdf, 0x4c], "ld1 {v16.2d, v17.2d}, [x10], 0x20"),
         ([0xa8, 0x85, 0x00, 0x4d], "st1 {v8.d}[1], [x13]"),
         ([0xac, 0x85, 0x00, 0x4d], "st1 {v12.d}[1], [x13]"),
         ([0xec, 0x85, 0x00, 0x4d], "st1 {v12.d}[1], [x15]"),
@@ -2824,8 +2824,8 @@ fn test_openblas_simd_loadstore() {
         ([0xa8, 0x85, 0x40, 0x4d], "ld1 {v8.d}[1], [x13]"),
         ([0xec, 0x85, 0x40, 0x4d], "ld1 {v12.d}[1], [x15]"),
         ([0x64, 0x84, 0x84, 0x4d], "st1 {v4.d}[1], [x3], x4"),
-        ([0x64, 0x84, 0x9f, 0x4d], "st1 {v4.d}[1], [x3], 8"),
-        ([0x24, 0xcd, 0xdf, 0x4d], "ld1r {v4.2d}, [x9], 8"),
+        ([0x64, 0x84, 0x9f, 0x4d], "st1 {v4.d}[1], [x3], 0x8"),
+        ([0x24, 0xcd, 0xdf, 0x4d], "ld1r {v4.2d}, [x9], 0x8"),
         ([0x60, 0x04, 0x81, 0x3c], "str q0, [x3], 0x10"),
         ([0x61, 0x00, 0x9f, 0x3c], "stur q1, [x3, -0x10]"),
         ([0xa0, 0x00, 0x9f, 0x3c], "stur q0, [x5, -0x10]"),
-- 
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