From 61541d356e6c9d378a85697778685b410fcbee1b Mon Sep 17 00:00:00 2001 From: iximeow Date: Mon, 17 Feb 2020 18:33:11 -0800 Subject: entirely replace armv7 operands Operands was an enum covering all forms of operands and data for each operand for all instructions. this is hard to iterate, and hard to work with when a single operand is the one of interest, so it's now replaced by an array of `Operand` enum instances like other architectures. in the course of this change, several forms of decoding are broken, while adding support for some earlier-unsupported multiplies and instructions like msr and clz also clearly note which document the comments mentioning page numbers/figures is referencing --- test/armv7.rs | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 153 insertions(+), 15 deletions(-) (limited to 'test') diff --git a/test/armv7.rs b/test/armv7.rs index 2a7ebe0..59f6000 100644 --- a/test/armv7.rs +++ b/test/armv7.rs @@ -1,5 +1,5 @@ use yaxpeax_arch::{Arch, Decoder, LengthedInstruction}; -use yaxpeax_arm::armv7::{ARMv7, Instruction, ConditionCode, Operands, Opcode, ShiftSpec}; +use yaxpeax_arm::armv7::{ARMv7, Instruction, ConditionCode, Operand, Opcode, Reg}; fn test_decode(data: [u8; 4], expected: Instruction) { let instr = ::Decoder::default().decode(data.to_vec()).unwrap(); @@ -30,7 +30,12 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::LDR(true, true, false), - operands: Operands::RegImm(12, 0x24), + operands: [ + Operand::Reg(Reg::from_u8(12)), + Operand::RegDisp(Reg::from_u8(15), 0x24), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -39,7 +44,12 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::LDR(true, true, false), - operands: Operands::RegImm(0, 0x10), + operands: [ + Operand::Reg(Reg::from_u8(0)), + Operand::RegDisp(Reg::from_u8(15), 0x10), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -48,7 +58,12 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::STR(false, true, true), - operands: Operands::TwoRegImm(13, 2, 4), + operands: [ + Operand::Reg(Reg::from_u8(2)), + Operand::RegDerefPostindexOffset(Reg::from_u8(13), 4), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -57,7 +72,12 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::STR(false, true, true), - operands: Operands::TwoRegImm(13, 0, 4), + operands: [ + Operand::Reg(Reg::from_u8(0)), + Operand::RegDerefPostindexOffset(Reg::from_u8(13), 4), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -66,7 +86,12 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::LDR(true, true, false), - operands: Operands::RegImm(3, 0x14), + operands: [ + Operand::Reg(Reg::from_u8(3)), + Operand::RegDisp(Reg::from_u8(15), 0x14), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -75,15 +100,84 @@ fn test_decode_str_ldr() { Instruction { condition: ConditionCode::AL, opcode: Opcode::LDR(true, true, false), - operands: Operands::RegImm(2, 0x14), + operands: [ + Operand::Reg(Reg::from_u8(2)), + Operand::RegDisp(Reg::from_u8(15), 0x14), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); } #[test] +fn test_synchronization() { + test_display( + [0x94, 0x8f, 0x8a, 0xe1], + "strex r8, r4, [r10]" + ); + test_display( + [0x9f, 0x8f, 0x9a, 0xe1], + "ldrex r8, [r10]" + ); + test_display( + [0x94, 0x2f, 0xa4, 0xe1], + "strexd r2, r4, r5, [r4]" + ); + test_display( + [0x9f, 0x2f, 0xb4, 0xe1], + "ldrexd r2, r3, [r4]" + ); + test_display( + [0x9f, 0x2f, 0xc4, 0xe1], + "strexb r2, pc, [r4]" + ); + test_display( + [0x9f, 0x2f, 0xd4, 0xe1], + "ldreb r2, [r4]" + ); + test_display( + [0x9f, 0x2f, 0xe4, 0xe1], + "strexh r2, pc, [r4]" + ); + test_display( + [0x9f, 0x2f, 0xf4, 0xe1], + "ldrexh r2, [r4]" + ); +} + +#[test] +fn test_str() { + test_display( + [0xb5, 0x53, 0x68, 0xe0], + "strht r5, [r8], -0x35" + ); +} + +#[test] +fn test_data_imm() { + test_display( + [0x12, 0x34, 0xa0, 0xe3], + "mov r3, 0x12000000" + ); + test_display( + [0x12, 0x44, 0x9c, 0xe3], + "orrs r4, ip, 0x12000000" + ); +} + +#[test] fn test_decode_misc() { test_display( + [0x13, 0x5f, 0x6f, 0xe1], + "clz r5, r3" + ); + test_display( + [0xc8, 0xac, 0x0b, 0xe1], + "smlabt fp, r8, ip, r10" + ); + test_display( [0x32, 0xff, 0x2f, 0xe1], "blx r2" ); @@ -104,7 +198,12 @@ fn test_decode_pop() { Instruction { condition: ConditionCode::AL, opcode: Opcode::LDR(true, false, false), - operands: Operands::TwoRegImm(13, 1, 4), + operands: [ + Operand::Reg(Reg::from_u8(1)), + Operand::RegDerefPostindexOffset(Reg::from_u8(13), 0x4), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -117,7 +216,12 @@ fn test_decode_pop() { Instruction { condition: ConditionCode::AL, opcode: Opcode::STM(false, true, true, false), - operands: Operands::RegRegList(13, 16624), + operands: [ + Operand::Reg(Reg::from_u8(13)), + Operand::RegList(16624), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -130,7 +234,12 @@ fn test_decode_pop() { Instruction { condition: ConditionCode::NE, opcode: Opcode::LDM(true, false, true, false), - operands: Operands::RegRegList(13, 33008), + operands: [ + Operand::Reg(Reg::from_u8(13)), + Operand::RegList(33008), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -147,7 +256,12 @@ fn test_decode_mov() { Instruction { condition: ConditionCode::AL, opcode: Opcode::MOV, - operands: Operands::TwoOperand(2, 13), + operands: [ + Operand::Reg(Reg::from_u8(2)), + Operand::Reg(Reg::from_u8(13)), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -156,7 +270,12 @@ fn test_decode_mov() { Instruction { condition: ConditionCode::AL, opcode: Opcode::MOV, - operands: Operands::RegImm(11, 0), + operands: [ + Operand::Reg(Reg::from_u8(11)), + Operand::Imm32(0), + Operand::Nothing, + Operand::Nothing, + ], s: false } ); @@ -164,6 +283,7 @@ fn test_decode_mov() { #[test] fn test_decode_arithmetic() { + /* test_decode( [0x18, 0x1d, 0x00, 0x00], Instruction { @@ -175,10 +295,12 @@ fn test_decode_arithmetic() { s: false } ); + */ test_display( [0x18, 0x1d, 0x00, 0x00], "andeq r1, r0, r8, lsl sp", ); + /* test_decode( [0x03, 0x30, 0x8f, 0xe0], Instruction { @@ -215,6 +337,7 @@ fn test_decode_arithmetic() { s: false } ); + */ } #[test] @@ -224,7 +347,12 @@ fn test_decode_mul() { Instruction { condition: ConditionCode::EQ, opcode: Opcode::MUL, - operands: Operands::MulThreeRegs(11, 12, 13), + operands: [ + Operand::Reg(Reg::from_u8(11)), + Operand::Reg(Reg::from_u8(12)), + Operand::Reg(Reg::from_u8(13)), + Operand::Nothing, + ], s: false } ); @@ -233,7 +361,12 @@ fn test_decode_mul() { Instruction { condition: ConditionCode::EQ, opcode: Opcode::MUL, - operands: Operands::MulThreeRegs(9, 0, 9), + operands: [ + Operand::Reg(Reg::from_u8(9)), + Operand::Reg(Reg::from_u8(0)), + Operand::Reg(Reg::from_u8(9)), + Operand::Nothing, + ], s: false } ); @@ -242,7 +375,12 @@ fn test_decode_mul() { Instruction { condition: ConditionCode::EQ, opcode: Opcode::MUL, - operands: Operands::MulThreeRegs(9, 4, 9), + operands: [ + Operand::Reg(Reg::from_u8(9)), + Operand::Reg(Reg::from_u8(4)), + Operand::Reg(Reg::from_u8(9)), + Operand::Nothing, + ], s: false } ); -- cgit v1.1