From fa24eedf78fb9fe2d87ac3f59763e25d3ba4462f Mon Sep 17 00:00:00 2001
From: rva3 <rva333@protonmail.com>
Date: Fri, 20 Feb 2026 03:45:01 +0200
Subject: support A1 encoding of several coprocessor instructions + SVC

initially was "implement MCR/MRC decoding", but expanded to include the
whole coprocessor space for completeness, and then SVC is right there
too.

Neon instructions in this space are still rejected, as neon support is
not really there yet.

Co-authored-by: iximeow <me@iximeow.net>
---
 tests/armv7/mod.rs | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

(limited to 'tests/armv7/mod.rs')

diff --git a/tests/armv7/mod.rs b/tests/armv7/mod.rs
index b878dd1..8f413ca 100644
--- a/tests/armv7/mod.rs
+++ b/tests/armv7/mod.rs
@@ -559,32 +559,74 @@ fn test_unconditional() {
 #[test]
 fn test_coproc() {
     test_armv5([0x12, 0x34, 0xcf, 0xfc], "stc2l p4, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x34, 0xcf, 0xec], "stcl p4, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x34, 0xcf, 0x0c], "stcleq p4, c3, [pc], {0x12}");
     test_armv5([0x12, 0x3d, 0xcf, 0xfc], "stc2l p13, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x3d, 0xcf, 0xec], "stcl p13, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x3d, 0xcf, 0x0c], "stcleq p13, c3, [pc], {0x12}");
     test_armv5([0x12, 0x34, 0xdf, 0xfc], "ldc2l p4, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x34, 0xdf, 0xec], "ldcl p4, c3, [pc], {0x12}");
+    test_armv5([0x12, 0x34, 0xdf, 0x0c], "ldcleq p4, c3, [pc], {0x12}");
     test_armv5([0x34, 0x78, 0xff, 0xfc], "ldc2l p8, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x78, 0xff, 0xec], "ldcl p8, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x78, 0xff, 0x0c], "ldcleq p8, c7, [pc], 0xd0");
     test_armv5([0x34, 0x7d, 0xff, 0xfc], "ldc2l p13, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x7d, 0xff, 0xec], "ldcl p13, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x7d, 0xff, 0x0c], "ldcleq p13, c7, [pc], 0xd0");
     test_invalid([0x34, 0x78, 0x1f, 0xfc]);
     test_armv5([0x34, 0x78, 0x9f, 0xfc], "ldc2 p8, c7, [pc], {0x34}");
+    test_armv5([0x34, 0x78, 0x9f, 0xec], "ldc p8, c7, [pc], {0x34}");
+    test_armv5([0x34, 0x78, 0x9f, 0x0c], "ldceq p8, c7, [pc], {0x34}");
     test_armv5([0x34, 0x7d, 0x9f, 0xfc], "ldc2 p13, c7, [pc], {0x34}");
+    test_armv5([0x34, 0x7d, 0x9f, 0xec], "ldc p13, c7, [pc], {0x34}");
+    test_armv5([0x34, 0x7d, 0x9f, 0x0c], "ldceq p13, c7, [pc], {0x34}");
     test_armv5([0x34, 0x78, 0xbf, 0xfc], "ldc2 p8, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x78, 0xbf, 0xec], "ldc p8, c7, [pc], 0xd0");
+    test_armv5([0x34, 0x78, 0xbf, 0x0c], "ldceq p8, c7, [pc], 0xd0");
     test_armv5([0x34, 0x78, 0xbf, 0xfd], "ldc2 p8, c7, [pc, 0xd0]!");
+    test_armv5([0x34, 0x78, 0xbf, 0xed], "ldc p8, c7, [pc, 0xd0]!");
+    test_armv5([0x34, 0x78, 0xbf, 0x0d], "ldceq p8, c7, [pc, 0xd0]!");
     test_armv5([0x34, 0x78, 0x9f, 0xfd], "ldc2 p8, c7, [pc, 0xd0]");
+    test_armv5([0x34, 0x78, 0x1f, 0xfd], "ldc2 p8, c7, [pc, -0xd0]");
+    test_armv5([0x34, 0x78, 0xdf, 0xfc], "ldc2l p8, c7, [pc], {0x34}");
     test_armv6([0x34, 0x78, 0x5a, 0xfc], "mrrc2 p8, 3, r7, r10, c4");
+    test_armv6([0x34, 0x78, 0x5a, 0xec], "mrrc p8, 3, r7, r10, c4");
+    test_armv6([0x34, 0x78, 0x5a, 0x0c], "mrrceq p8, 3, r7, r10, c4");
     test_armv6([0x34, 0x7d, 0x5a, 0xfc], "mrrc2 p13, 3, r7, r10, c4");
+    test_armv6([0x34, 0x7d, 0x5a, 0xec], "mrrc p13, 3, r7, r10, c4");
+    test_armv6([0x34, 0x7d, 0x5a, 0x0c], "mrrceq p13, 3, r7, r10, c4");
     // Rt/Rt2 may not be r15
     test_invalid([0x34, 0x78, 0x5f, 0xfc]);
+    test_invalid([0x34, 0x7d, 0x1f, 0x0c]); // op1 = 00000x => undefined
     test_armv6([0x34, 0x78, 0x4a, 0xfc], "mcrr2 p8, 3, r7, r10, c4");
+    test_armv6([0x34, 0x78, 0x4a, 0xec], "mcrr p8, 3, r7, r10, c4");
+    test_armv6([0x34, 0x78, 0x4a, 0x0c], "mcrreq p8, 3, r7, r10, c4");
     test_armv6([0x34, 0x7d, 0x4a, 0xfc], "mcrr2 p13, 3, r7, r10, c4");
+    test_armv6([0x34, 0x7d, 0x4a, 0xec], "mcrr p13, 3, r7, r10, c4");
+    test_armv6([0x34, 0x7d, 0x4a, 0x0c], "mcrreq p13, 3, r7, r10, c4");
     // Rt/Rt2 may not be r15
     test_invalid([0x34, 0x78, 0x4f, 0xfc]);
     test_armv5([0x34, 0x78, 0x4f, 0xfe], "mcr2 p8, 2, r7, c15, c4, 1");
     test_armv5([0x34, 0x7d, 0x4f, 0xfe], "mcr2 p13, 2, r7, c15, c4, 1");
+    test_armv5([0x34, 0x7d, 0x4f, 0xee], "mcr p13, 2, r7, c15, c4, 1");
+    test_armv5([0x34, 0x7d, 0x4f, 0x0e], "mcreq p13, 2, r7, c15, c4, 1");
     test_armv5([0x34, 0x78, 0x5f, 0xfe], "mrc2 p8, 2, r7, c15, c4, 1");
     test_armv5([0x34, 0x7d, 0x5f, 0xfe], "mrc2 p13, 2, r7, c15, c4, 1");
+    test_armv5([0x34, 0x7d, 0x5f, 0xee], "mrc p13, 2, r7, c15, c4, 1");
+    test_armv5([0x34, 0x7d, 0x5f, 0x0e], "mrceq p13, 2, r7, c15, c4, 1");
     test_armv5([0x24, 0x78, 0x5f, 0xfe], "cdp2 p8, 5, c7, c15, c4, 1");
     test_armv5([0x24, 0x7d, 0x5f, 0xfe], "cdp2 p13, 5, c7, c15, c4, 1");
+    test_armv5([0x24, 0x7d, 0x5f, 0xee], "cdp p13, 5, c7, c15, c4, 1");
+    test_armv5([0x24, 0x7d, 0x5f, 0x0e], "cdpeq p13, 5, c7, c15, c4, 1");
     test_armv5([0x24, 0x78, 0x4f, 0xfe], "cdp2 p8, 4, c7, c15, c4, 1");
     test_armv5([0x24, 0x7d, 0x4f, 0xfe], "cdp2 p13, 4, c7, c15, c4, 1");
+    test_armv5([0x24, 0x7d, 0x4f, 0xee], "cdp p13, 4, c7, c15, c4, 1");
+    test_armv5([0x24, 0x7d, 0x4f, 0x0e], "cdpeq p13, 4, c7, c15, c4, 1");
+}
+
+#[test]
+fn test_svc() {
+    test_display([0x24, 0x7d, 0x4f, 0x0f], "svceq 0x4f7d24");
 }
 
 #[test]
-- 
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