From bbbb546ee0b73d295be891b1b2e0e5a18cbfd3d1 Mon Sep 17 00:00:00 2001 From: Brandon Ros Date: Fri, 3 Jul 2026 20:48:35 -0400 Subject: fix thumb2 TBH decode: wrong opcode and register-shift operand the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. --- tests/armv7/thumb.rs | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'tests') diff --git a/tests/armv7/thumb.rs b/tests/armv7/thumb.rs index 8c1885d..6384af7 100644 --- a/tests/armv7/thumb.rs +++ b/tests/armv7/thumb.rs @@ -4325,3 +4325,40 @@ fn test_decode_shift_reg_32b_cases() { "ror.w r1, r2, r3" ); } + +#[test] +fn test_decode_tbb_tbh_cases() { + test_display( + &[0xdf, 0xe8, 0x13, 0xf0], + "tbh [pc, r3, lsl 1]" + ); + test_display( + &[0xdf, 0xe8, 0x0b, 0xf0], + "tbb [pc, fp]" + ); +} + +#[test] +fn test_decode_tbh_operand_shape() { + use yaxpeax_arm::armv7::{Opcode, Operand, RegShiftStyle, ShiftStyle}; + + let mut reader = yaxpeax_arch::U8Reader::new(&[0xdf, 0xe8, 0x13, 0xf0][..]); + let inst = InstDecoder::default_thumb().decode(&mut reader).unwrap(); + assert_eq!(inst.opcode, Opcode::TBH); + match inst.operands[0] { + Operand::RegDerefPreindexRegShift(base, shift, add, wback) => { + assert_eq!(base.number(), 15); + assert!(add); + assert!(!wback); + match shift.into_shift() { + RegShiftStyle::RegImm(s) => { + assert_eq!(s.shiftee().number(), 3); + assert_eq!(s.stype(), ShiftStyle::LSL); + assert_eq!(s.imm(), 1); + } + RegShiftStyle::RegReg(_) => panic!("TBH index must be a register+immediate shift"), + } + } + other => panic!("unexpected TBH operand: {:?}", other), + } +} -- cgit v1.1