## 0.2.5
* fix decoding armv8 a64 hint instructions
  - in some cases the displayed hint instruction was incorrect
  - additionally, the `op1` field in decoded instructions included two more
    bits than it should
  - thanks to belovdv for the patch!
* improve decoding of armv8 a64 msr instructions
  - decoding of the `PstateField` immediate value was just terribly wrong.
  - this should be improved to more precisely match section `C5.1.3`
    "architectural hints, barriers and CLREX, and PSTATE access", but least
    fields are decoded properly.

## 0.2.4
* fix `no_std` builds
* several fixes relating to arm- and thumb-mode v7 branch offset decoding
  - thanks to both ehntoo and jam1garner for these!
* make `ShiftStyle::into_shift` public. it was private as an oversight; this is
  a useful conversion involved in programmatic handling of instructions.
  - thanks to wscp for catching this!

## 0.2.3
* add differential tests, initial impl only tests against capstone

## 0.2.2
* fix docs typo.

## 0.2.1
* README updates.

## 0.2.0
* added documentation to all public members.
* fix tests incorrectly expecting `lsl #0` in memory operands where it would have no effect
* remove some redundant `a64` operand kinds:
  - `RegOffset` is now `RegPreIndex` with no writeback.
  - `Offset` was a duplicate of `PCOffset`, and all uses have been so-renamed.

## 0.1.4
* add or fix many a64 instructions, extend support up through armv8.5.
  - some disassembly and optional elements of instruction text does not match
    the arm manual, but instruction data should be correct across the board.
  - SVE and SVE2 are not yet supported, and return `IncompleteDecoder` errors.

## 0.1.3
* same as 0.1.2, but fixes a few compilation warnings that snuck in too.

## 0.1.2
* fix some instructions in aarch64 decoding panicking with "unreachable"
  instead of returning an `Err(DecodeError::Incomplete)`. similarly, some
  instructions panicked instead of returning `InvalidOpcode` or `InvalidOperand`
  as they should.
* fix some instructions in armv7 decoding or display panicking instead of
  displaying a valid instruction, or returning a decode error.

... subsequently yanked because some compilation warnings ended up in this version.

## 0.1.1
* fix incorrect `yaxpeax_arch::Arch` impl for `std`-enabled builds
  (DecodeError did not implement `std::error::Error` in those build environments)

## 0.1.0
* target yaxpeax-arch 0.2.0

## 0.0.6
* fix incorrect markdown in README.md

## 0.0.5
* add thumb/thumb2 decoders

these decoders are considered "mostly correct" and "mostly complete". notably,
system instructions are less well-tested (particularly `mrs`, `cps`, and
similar), and the NEON extensions are still unsupported. NEON in particular
yield `DecodeError::Incomplete`. if you, the user, see `Incomplete`, that is a
`yaxpeax-arm` error!

`yaxpeax-arm` differs from the ARM manual's assembly syntax in a few ways:
* `.w` suffixes are best-effort.
* `addw`/`subw` are written `add.w`/`sub.w` for consistency with other wide instructions.
* `adr` with added/subtracted offset are shown as `add`/`sub`
* testing is not as exhaustive as is possible for ARM; errors may yet exist

at this time, if-then instructions (`IT`) are decoded, but the decoder has no
notion of "in an `IT` block or not", so following conditional instructions are
not yet conditional.

this all said, for armv4/thumb decoding, the implementation here is probably
close to correct. for armv6+/thumb2, aside from these notes, the implementation
here is ... hopefully ... close to correct.

* add clear rules by which `yaxpeax-arm` will be versioned 0.1 or 1.0. (see README)

## 0.0.4
* bump yaxpeax-arch, no functional change

## 0.0.3
`Instruction`, `Opcode`, and `Operand` are now a useful model of decoded
operations.
* `Operands`, plural, the enum of operands in the instruction, is now gone in
  favor of `Operand` that describe one operand of the instruction
* `Instruction` no longer include operand attributes like "add", "index", or "wback"
* better (not quite complete) support for non-user instructions and coprocessor instructions
* instructions operating on status registers through masks are now directly supported
* first brush of arm-version-specific decoder feature selection
* fix several preindex/postindex reversals

## 0.0.2
last revison that's sufficient for disassembly and really nothing else