## 0.5.0

* ARMv7 instructions now impl Copy and Clone, matching A64 instructions and so
  many enums/structures from decoded instructions.
* ARMv7: expand support for coprocessor, SVC instructions. (thank you @rva333!)
  * support non-Thumb encoding of SVC
  * support non-`*2` forms of coprocessor instructions
  * collapse `*2` encoding choice for coprocessor instructions into a paramter
    on the opcode (rather than distinct opcodes)
* thumb2: use correct opcode table for parallel addition/subtractions
  * the decoder reused the non-thumb encoding table, but thumb opcode/sizes are
    encoded in a different order.
* thumb2: write condition code *before* .w suffix
  * this fixes nonsense "opcodes" like "b.weq", which should have been "beq.w"
* thumb2: `ldrexd` was off by one in looking up an opcode
* thumb2: pkhtb/pkhbt distinction was off by one bit
* thumb2: `mrs` destinations, which should have been a mask of the current (or
  saved) program status register, was reported as a banked GPR.
* thumb2: fixed much confusion about `msr` sources, similar to `mrs`.
* thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*`
* thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register)
* thumb2: rfeia and rfedb were decoded backwards. likewise for srsia and srsdb
* thumb2: unknown wide hints are decoded as `hint` like other cases in ARM,
  rather than rejected as invalid
* thumb2: support ARMv8 hints PACBTI, BTI, ESB, PAC, and AUT
* thumb2: fix `mrc`, `mrc2` use of register number "15", which means apsr_nzcv,
  rather than pc
* thumb2: several instructions which decode an explicit rotate operand now do so
  into a distinct Operand::Ror (sxth, uxth, stxb16, utxb16, sxtb, uxtb)
* ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT`
  (formatted as any of `tt`, `ttt`, `tta`, `ttat`)
* ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions,
  meaning some MRC/MCR/CDP instructions have become `DecodeError::Incomplete`

several fixes from @Grond66:
* ARMv7: support the RRX rotate mode.
* ARMv7: added `armv7::InstDecoder::in_thumb_mode` to read back if an ARMv7
  decoder is operating in thumb mode.
* ARMv7: fix incorrect handling of registers lsr or asr by an immediate 32.
  yaxpeax-arm incorrectly reported a shift of 0, but should have reported 32.
* ARMv7: reject unconditional instructions with op1=1111xxxx. these were
  decoded as CDP, MCR, or MRC when the bit pattern is actually undefined.
* ARMv7: fix inverted reserved bit test for some ldr*/str* (immediate) forms.
* ARMv7: fix several issues with data processing instructions:
  * CMP/CMN decoded "three operands" in some cases when they only have two.
  * TST/TEQ decoded "three operands" in some cases when they only have two.
* ARMv7: do not print the "s" suffix for instructions that unconditionally set flags.

as well as thumb2 fixes from @brandonros:
* thumb2: wide store encodings were very confused about offset widths.
* thumb2: movw/movt incorrectly reassembled 16-bit immediates into 20-bit immediates.
* thumb2: some instructions had outright incorrect opcodes:
  * ror (immediate) was decoded as asr,
  * mvn (immediate) was decoded as mov,
  * sxtab was decoded as sxtah,
  * lsl, lsr, asr, ror were determining opcode from an incorrect bitfield,
  * tbh was decoded as an shifted tbb,
* thumb2: (un)signed extend-and-rotate loaded an incorrect field for rotate,
* thumb2: preload hints (PLD, PLI) were over-eagerly decoded
  namely, ldrb{t} and ldrh{t} into pc are .. weird .. but just weird.
* thumb2: preload data reported two operands when it has one
  (the "first operand" was the Rd=r15 operand which makes them preload in the first place)

thank you for the patches!

additionally, one of the cases where thumb-mode SIMD instructions should have
been rejected with DecodeError::Incomplete instead fell through to report a
successful decode result of the provided instruction. this now results in
DecodeError::Incomplete as expected.

when decoding into an instruction multiple times (such as `Decoder::decode_into`)
the provided instruction would be left in an incoherent state mostly consiting
of its previous data. when decoding as through `Decoder::decode`, the returned
instruction had opcode `Invalid`.

## 0.4.0

* ARMv7 and A64 `Opcode` and `Operand` are now `#[non_exhaustive]`.
  - additions to both enums may happen across minor releases in the future, but
    will not happen across patch releases.
  - this attribute is removed if the crate is built without default features.
    expected uses include validating match completeness when testing
    opcode-analyzing code against a specific version of `yaxpeax-arm`. there is
    a more comprehensive discussion of this feature on its entry in
    `Cargo.toml`.
* fully support PAC instructions
* support hinted branch instructions from ARMv8.7
* inline some armv7 decode helper functions
  - this actually makes the armv7 decoder both faster *and* smaller. measured
    against tdfx_dri.so, this takes decode throughput from ~410mb/s to ~709mb/s
    while shedding about 100 bytes of code from the decoder's footprint
* fix some issues with tag instruction decoding
  - the raw tag offset was reported, rather than the shifted-by-four value that
    corresponds to a real address
  - ldg was displayed as "ldm" (thank you @martin-fink!)

## 0.3.1

* fix no-std transitively depending on std still
  - thank you @encounter for the patch!

## 0.3.0

* major version bump of yaxpeax-arch (0.2.7 -> 0.3.1)
  - while there is no direct API breakage of yaxpeax-arch, typical use of the
    yaxpeax crates would have issues with their yaxpeax-arch dependency not
    matching the transitive dependency through specific decoder crates. so, major
    version bump it is!

## 0.2.6

* aarch64: add support for `udf` (`0000_0000_0000_0000_<imm16>`)
  - thank you @martin-fink!

## 0.2.5
* fix decoding armv8 a64 hint instructions
  - in some cases the displayed hint instruction was incorrect
  - additionally, the `op1` field in decoded instructions included two more
    bits than it should
  - thanks to belovdv for the patch!
* improve decoding of armv8 a64 msr instructions
  - decoding of the `PstateField` immediate value was just terribly wrong.
  - this should be improved to more precisely match section `C5.1.3`
    "architectural hints, barriers and CLREX, and PSTATE access", but least
    fields are decoded properly.

## 0.2.4
* fix `no_std` builds
* several fixes relating to arm- and thumb-mode v7 branch offset decoding
  - thanks to both ehntoo and jam1garner for these!
* make `ShiftStyle::into_shift` public. it was private as an oversight; this is
  a useful conversion involved in programmatic handling of instructions.
  - thanks to wscp for catching this!

## 0.2.3
* add differential tests, initial impl only tests against capstone

## 0.2.2
* fix docs typo.

## 0.2.1
* README updates.

## 0.2.0
* added documentation to all public members.
* fix tests incorrectly expecting `lsl #0` in memory operands where it would have no effect
* remove some redundant `a64` operand kinds:
  - `RegOffset` is now `RegPreIndex` with no writeback.
  - `Offset` was a duplicate of `PCOffset`, and all uses have been so-renamed.

## 0.1.4
* add or fix many a64 instructions, extend support up through armv8.5.
  - some disassembly and optional elements of instruction text does not match
    the arm manual, but instruction data should be correct across the board.
  - SVE and SVE2 are not yet supported, and return `IncompleteDecoder` errors.

## 0.1.3
* same as 0.1.2, but fixes a few compilation warnings that snuck in too.

## 0.1.2
* fix some instructions in aarch64 decoding panicking with "unreachable"
  instead of returning an `Err(DecodeError::Incomplete)`. similarly, some
  instructions panicked instead of returning `InvalidOpcode` or `InvalidOperand`
  as they should.
* fix some instructions in armv7 decoding or display panicking instead of
  displaying a valid instruction, or returning a decode error.

... subsequently yanked because some compilation warnings ended up in this version.

## 0.1.1
* fix incorrect `yaxpeax_arch::Arch` impl for `std`-enabled builds
  (DecodeError did not implement `std::error::Error` in those build environments)

## 0.1.0
* target yaxpeax-arch 0.2.0

## 0.0.6
* fix incorrect markdown in README.md

## 0.0.5
* add thumb/thumb2 decoders

these decoders are considered "mostly correct" and "mostly complete". notably,
system instructions are less well-tested (particularly `mrs`, `cps`, and
similar), and the NEON extensions are still unsupported. NEON in particular
yield `DecodeError::Incomplete`. if you, the user, see `Incomplete`, that is a
`yaxpeax-arm` error!

`yaxpeax-arm` differs from the ARM manual's assembly syntax in a few ways:
* `.w` suffixes are best-effort.
* `addw`/`subw` are written `add.w`/`sub.w` for consistency with other wide instructions.
* `adr` with added/subtracted offset are shown as `add`/`sub`
* testing is not as exhaustive as is possible for ARM; errors may yet exist

at this time, if-then instructions (`IT`) are decoded, but the decoder has no
notion of "in an `IT` block or not", so following conditional instructions are
not yet conditional.

this all said, for armv4/thumb decoding, the implementation here is probably
close to correct. for armv6+/thumb2, aside from these notes, the implementation
here is ... hopefully ... close to correct.

* add clear rules by which `yaxpeax-arm` will be versioned 0.1 or 1.0. (see README)

## 0.0.4
* bump yaxpeax-arch, no functional change

## 0.0.3
`Instruction`, `Opcode`, and `Operand` are now a useful model of decoded
operations.
* `Operands`, plural, the enum of operands in the instruction, is now gone in
  favor of `Operand` that describe one operand of the instruction
* `Instruction` no longer include operand attributes like "add", "index", or "wback"
* better (not quite complete) support for non-user instructions and coprocessor instructions
* instructions operating on status registers through masks are now directly supported
* first brush of arm-version-specific decoder feature selection
* fix several preindex/postindex reversals

## 0.0.2
last revison that's sufficient for disassembly and really nothing else