From 7d077f45b7e4a9776ac516da36381861e0d7e7bd Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sat, 12 Apr 2025 13:29:20 -0700
Subject: initial instruction extender support, more system instructions

---
 src/display.rs | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/display.rs')

diff --git a/src/display.rs b/src/display.rs
index eb19107..a9e5e49 100644
--- a/src/display.rs
+++ b/src/display.rs
@@ -714,6 +714,8 @@ impl fmt::Display for Opcode {
             Opcode::DcInvA => { f.write_str("dcinva") },
             Opcode::DcCleanInvA => { f.write_str("dccleaninva") },
             Opcode::DcZeroA => { f.write_str("dczeroa") },
+            Opcode::DcKill => { f.write_str("dckill") },
+            Opcode::IcKill => { f.write_str("ickill") },
             Opcode::L2Fetch => { f.write_str("l2fetch") },
             Opcode::DmSyncHt => { f.write_str("dmsyncht") },
             Opcode::SyncHt => { f.write_str("syncht") },
@@ -792,6 +794,7 @@ impl fmt::Display for Opcode {
             Opcode::Iassignr => { f.write_str("iassignr") },
             Opcode::Icdatar => { f.write_str("icdatar") },
             Opcode::Ictagr => { f.write_str("ictagr") },
+            Opcode::Ictagw => { f.write_str("ictagw") },
             Opcode::Icinvidx => { f.write_str("icinvidx") },
 
             Opcode::SubAsl => { f.write_str("subasl") },
@@ -1051,6 +1054,9 @@ impl fmt::Display for Operand {
             Operand::ImmU32 { imm } => {
                 write!(f, "#{:}", imm)
             }
+            Operand::Immext { imm } => {
+                write!(f, "##{:#x}", imm)
+            }
             Operand::RegShiftOffset { base, shift, offset } => {
                 write!(f, "r{}<<{} + {:#x}", base, shift, offset)
             }
-- 
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