From e90196a82884abcbd950f17a457e0109fa1ca1b5 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Wed, 16 Jan 2019 03:49:00 -0800
Subject: initial commit

---
 src/lib.rs | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 src/lib.rs

(limited to 'src/lib.rs')

diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 0000000..1ef6f13
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1,46 @@
+extern crate yaxpeax_arch;
+
+use yaxpeax_arch::{Arch, Decodable, LengthedInstruction};
+
+#[derive(Debug)]
+pub enum Opcode {
+    NOP
+}
+
+#[derive(Debug)]
+pub struct Instruction {
+    pub opcode: Opcode
+}
+
+impl LengthedInstruction for Instruction {
+    type Unit = <PIC24 as Arch>::Address;
+    fn len(&self) -> Self::Unit {
+        3 // ish
+    }
+}
+
+impl Decodable for Instruction {
+    fn decode<'a, T: IntoIterator<Item=&'a u8>>(bytes: T) -> Option<Self> {
+        let mut blank = Instruction { opcode: Opcode::NOP };
+        match blank.decode_into(bytes) {
+            Some(_) => Some(blank),
+            None => None
+        }
+    }
+    fn decode_into<'a, T: IntoIterator<Item=&'a u8>>(&mut self, bytes: T) -> Option<()> {
+        match bytes.into_iter().next() {
+            Some(0x00) => {
+                self.opcode = Opcode::NOP;
+                Some(())
+            },
+            _ => None
+        }
+    }
+}
+
+pub struct PIC24;
+impl Arch for PIC24 {
+    type Address = u32;
+    type Instruction = Instruction;
+    type Operand = ();
+}
-- 
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