From 58913fc4e1bb153fe9d8735164ef922f71c2fa97 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 16 Dec 2023 16:12:25 -0800 Subject: fix hreset being disassembled as having second operand of "Nothing" just report it having one operand... --- CHANGELOG | 7 +++++++ src/long_mode/mod.rs | 1 + src/protected_mode/mod.rs | 1 + src/real_mode/mod.rs | 1 + test/long_mode/mod.rs | 3 +++ test/protected_mode/mod.rs | 3 +++ test/real_mode/mod.rs | 9 +++++++++ 7 files changed, 25 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 4653f57..d420ed0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,10 @@ +## 1.2.2 + +* fix `hreset` reporting two operands, with a second operand of `Nothing`. + this is not exactly a *bug*, there is in fact no second operand and libraries + probably ought to handle `Nothing` identically to having no operand reported + at all. but `yaxpeax-x86` intends to not report superfluous operands. + ## 1.2.1 * fix incorrect register numbers used in `RegSpec::r12()` and `RegSpec::r13()` diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 439417a..9bc9f0b 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -8812,6 +8812,7 @@ fn read_operands< instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; + instruction.operand_count = 1; } OperandCase::G_mm_Edq => { instruction.regs[0].bank = RegisterBank::MM; diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs index 200e12f..0d125eb 100644 --- a/src/protected_mode/mod.rs +++ b/src/protected_mode/mod.rs @@ -8668,6 +8668,7 @@ fn read_operands< instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; + instruction.operand_count = 1; } OperandCase::G_mm_Ed => { instruction.regs[0].bank = RegisterBank::MM; diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs index 6765c1e..68ab6dd 100644 --- a/src/real_mode/mod.rs +++ b/src/real_mode/mod.rs @@ -8674,6 +8674,7 @@ fn read_operands< instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; + instruction.operand_count = 1; } OperandCase::G_mm_Ed => { instruction.regs[0].bank = RegisterBank::MM; diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs index c0ec1a5..8cb032c 100644 --- a/test/long_mode/mod.rs +++ b/test/long_mode/mod.rs @@ -3463,6 +3463,9 @@ fn test_keylocker() { #[test] fn from_llvm() { test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); + let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); + let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); + assert_eq!(hreset.operand_count(), 1); } #[test] diff --git a/test/protected_mode/mod.rs b/test/protected_mode/mod.rs index fd77b5e..0f3a6ff 100644 --- a/test/protected_mode/mod.rs +++ b/test/protected_mode/mod.rs @@ -3138,6 +3138,9 @@ fn test_keylocker() { #[test] fn from_llvm() { test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); + let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); + let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); + assert_eq!(hreset.operand_count(), 1); } #[test] diff --git a/test/real_mode/mod.rs b/test/real_mode/mod.rs index bc045d8..c5b1548 100644 --- a/test/real_mode/mod.rs +++ b/test/real_mode/mod.rs @@ -18414,6 +18414,15 @@ fn test_invalid_sequences() { } +// some test cases are best just lifted from llvm or gcc. +#[test] +fn from_llvm() { + test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); + let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); + let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); + assert_eq!(hreset.operand_count(), 1); +} + #[test] fn from_reports() { // negative compressed evex displacements should not overflow and panic -- cgit v1.1