From c22532de02b9b050c6a6f5a995a33516201d69b1 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 3 Aug 2020 21:46:30 -0700
Subject: cmc and int1

---
 src/long_mode/display.rs |  2 ++
 src/long_mode/mod.rs     | 15 ++++++++++-----
 test/long_mode/mod.rs    |  2 ++
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs
index e2943d3..a4a4d79 100644
--- a/src/long_mode/display.rs
+++ b/src/long_mode/display.rs
@@ -497,6 +497,7 @@ const MNEMONICS: &[&'static str] = &[
     "ltr",
     "verr",
     "verw",
+    "cmc",
     "clc",
     "stc",
     "cli",
@@ -1888,6 +1889,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color
             Opcode::SHUFPS |
             Opcode::PMOVMSKB |
             Opcode::LDDQU |
+            Opcode::CMC |
             Opcode::CLC |
             Opcode::CLI |
             Opcode::CLD |
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 6d42496..c6c4135 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -784,6 +784,7 @@ pub enum Opcode {
     LTR,
     VERR,
     VERW,
+    CMC,
     CLC,
     STC,
     CLI,
@@ -3505,10 +3506,9 @@ pub enum OperandCode {
     DX_Xv,
     AH,
     AX_Xv,
-    // DX_AX,
-    // Ev_Ivs,
     Ew_Sw,
     Fw,
+    I_1,
     I_3,
     Ib,
     Ibs,
@@ -3522,7 +3522,7 @@ pub enum OperandCode {
     Yb_AL,
     Yb_Xb,
     Yv_AX,
-    Yv_Xv,
+    Yv_Xv = OperandCodeBuilder::new().special_case(50).bits(),
 
     x87_d8 = OperandCodeBuilder::new().special_case(31).bits(),
     x87_d9 = OperandCodeBuilder::new().special_case(32).bits(),
@@ -5209,13 +5209,13 @@ const OPCODES: [OpcodeRecord; 256] = [
 // 0xf0
     OpcodeRecord(Interpretation::Prefix, OperandCode::Nothing),
     // ICEBP?
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::INT), OperandCode::I_1),
     OpcodeRecord(Interpretation::Prefix, OperandCode::Nothing),
     OpcodeRecord(Interpretation::Prefix, OperandCode::Nothing),
 // 0xf4
     OpcodeRecord(Interpretation::Instruction(Opcode::HLT), OperandCode::Nothing),
     // CMC
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CMC), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf6),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf7),
     OpcodeRecord(Interpretation::Instruction(Opcode::CLC), OperandCode::Nothing),
@@ -6230,6 +6230,11 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
             instruction.operand_count = 0;
             return Ok(());
         },
+        OperandCode::I_1 => {
+            instruction.imm = 1;
+            instruction.operands[0] = OperandSpec::ImmU8;
+            instruction.operand_count = 1;
+        }
         OperandCode::Unsupported => {
             return Err(DecodeError::IncompleteDecoder);
         }
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index a359a5c..bd5008c 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -1211,6 +1211,8 @@ fn test_bitwise() {
 
 #[test]
 fn test_misc() {
+    test_display(&[0xf1], "int 0x1");
+    test_display(&[0xf5], "cmc");
     test_display(&[0xc8, 0x01, 0x02, 0x03], "enter 0x201, 0x3");
     test_display(&[0xc9], "leave");
     test_display(&[0xca, 0x12, 0x34], "retf 0x3412");
-- 
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