From 87dc48adcce4e80aa98a2867edacc023579fc4c4 Mon Sep 17 00:00:00 2001 From: iximeow Date: Thu, 19 Feb 2026 02:14:57 +0000 Subject: add behavior information for x86_64 instructions this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders. --- CHANGELOG | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index b36e7f6..732b850 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,5 +1,8 @@ ## 2.1.0 +* x86-64, x86-32, and x86-16 instructions now have associated behavior information + (operand read/write, exceptions, privilege levels) accessible via `Instruction::behavior()`. + the new `behavior` modules include examples and further discussion of the new APIs. * `InstDecoder` for all execution modes now has many more feature flags. * `InstDecoder::default` still constructs a decoder that decodes all supported instructions. * more ISA extensions can be individually selected for decoding support, though note @@ -9,6 +12,8 @@ * removed 3DNow support from AMD uarch-specific decoders after K10 * RegSpec register helpers to construct RegSpec from register numbers are now const fn (RegSpec::xmm, RegSpec::q, RegSpec::d, RegSpec::st, etc) +* new crate feature flag, `unstable`, for library features that may see + breaking changes across semver-compatible releases. * for uarch-specific decoding, there is now a feature bit for Intel Key Locker. this corrects an issue where Key Locker instructions would decode under AMD-specific decoders. * push-immediate, pushf, popf, pusha, popa, enter, leave, and xlat now all report a correct memory -- cgit v1.1