From a049351c5d512710f557ffb45ee6391fc86a3dc6 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 12 Apr 2026 01:03:47 +0000 Subject: fix table management instructions' ({l,s}{g,i,l}dt) mem_size these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! --- CHANGELOG | 2 ++ 1 file changed, 2 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 8d88ec7..540a5bf 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -10,6 +10,8 @@ * push-immediate, pushf, popf, enter, leave, and xlat now all report a correct memory access size, fixing the prior behavior of reporting no memory access size at all +* table load/store instructions (lgdt, lidt, lldt, sgdt, sidt, sldt) have correct (mode-dependent) + memory access sizes, rather than incorrectly varying on operand-size overrides. * 64-bit mode: mov seg-to-reg uses 32-bit GPRs for the destination rather than 16-bit. * this is more accurate to the semantic of the instruction, which is why other disassemblers report it this way; for register destinations specifically the segment selector is -- cgit v1.1