From ab51fd1b2c7cf1b7bb6f84c5b07e06245f6b3d99 Mon Sep 17 00:00:00 2001 From: iximeow Date: Mon, 24 Jul 2023 06:41:02 -0700 Subject: fix handling of lar/lsl source register --- CHANGELOG | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 81a1f46..091aa06 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -25,6 +25,11 @@ encodings and bitness * in some cases, instructions loading a single-precision float reported 8-byte loads * in some cases, instructions loading a double-precision float reported 4-byte loads +* fix register sizes for lar/lsl + * 16 bits are read from the source register, but x86 docs state that the + source register is written as 16-bit, 32-bit, or 64-bit, as prefixes dictate. + memory is always written as `word [addr]`, which was correct before and + remains the case. ## 1.1.5 * fix several typos across crate docs - thank you Bruce! (aka github user waywardmonkeys) -- cgit v1.1