From f900cfe558b97d187226c6e0791ad8992ba8f4a0 Mon Sep 17 00:00:00 2001 From: iximeow Date: Fri, 8 May 2026 01:19:33 +0000 Subject: working through a bunch of avx512 stuff, regspec constructors are const --- CHANGELOG | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index f8197d0..b42570b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -7,6 +7,8 @@ even when their corresponding extension is not selected. * added uarch-specific decoders for Zen 2, Zen 3, Zen 4, and Zen 5 * removed 3DNow support from AMD uarch-specific decoders after K10 +* RegSpec register helpers to construct RegSpec from register numbers are now const fn + (RegSpec::xmm, RegSpec::q, RegSpec::d, RegSpec::st, etc) * for uarch-specific decoding, there is now a feature bit for Intel Key Locker. this corrects an issue where Key Locker instructions would decode under AMD-specific decoders. * push-immediate, pushf, popf, enter, leave, and xlat now all report a correct memory @@ -32,6 +34,8 @@ always decoded as ymm. * vmaskmovqdu now reports a memory access size for the implied write to ds:[rdi/edi/di]. * correct swapped operand order of 0xD6-opcode movq. in 32/16-bit, fix this opcode being decoded as vmovd. +* reject so many invalid AVX512 encodings (instructions which do not support broadcast, + or rounding, or require W=0/W=1, etc). * some instructions (such as invept, invvpid) were accepted by uarch-specific deocders when they should not have been. -- cgit v1.1