From 87dc48adcce4e80aa98a2867edacc023579fc4c4 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Thu, 19 Feb 2026 02:14:57 +0000
Subject: add behavior information for x86_64 instructions

this is a squash of a few months' hacking, including but not limited to
what eventually got extracted into
https://git.iximeow.net/asmlinator/about/

the path here is generally not historically interesting, and the vast
majority of this diff is very particular static data tables
(BehaviorDigests and implicit operand lists)

`src/long_mode/behavior.rs` will more or less be directly adapted into
versions for x86-32 and x86-16, similar to the instruction decoders.
---
 src/long_mode/mod.rs | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

(limited to 'src/long_mode/mod.rs')

diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 081d20f..c477b16 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -3,6 +3,8 @@ mod evex;
 #[cfg(feature = "fmt")]
 mod display;
 pub mod uarch;
+#[cfg(feature = "behavior")]
+pub mod behavior;
 
 pub use crate::MemoryAccessSize;
 use crate::{Address, Word};
@@ -304,6 +306,13 @@ impl RegSpec {
         r12b => 12, r13b => 13, r14b => 14, r15b => 15
     );
 
+    register!(CR,
+        cr0 => 0, cr1 => 1, cr2 => 2, cr3 => 3,
+        cr4 => 4, cr5 => 5, cr6 => 6, cr7 => 7,
+        cr8 => 8, cr9 => 9, cr10 => 10, cr11 => 11,
+        cr12 => 12, cr13 => 13, cr14 => 14, cr15 => 15
+    );
+
     #[inline]
     pub const fn zmm0() -> RegSpec {
         RegSpec { bank: RegisterBank::Z, num: 0 }
@@ -1088,6 +1097,7 @@ const XSAVE: [Opcode; 10] = [
 /// an `x86_64` opcode. there sure are a lot of these.
 #[allow(non_camel_case_types)]
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "_debug_internal_asserts", derive(strum::EnumCount))]
 #[non_exhaustive]
 #[repr(u32)]
 pub enum Opcode {
@@ -1190,8 +1200,11 @@ pub enum Opcode {
     LEA,
     NOP,
     PREFETCHNTA,
+    /// this variant was named incorrectly and will change to `PREFETCHT0` in the future.
     PREFETCH0,
+    /// this variant was named incorrectly and will change to `PREFETCHT1` in the future.
     PREFETCH1,
+    /// this variant was named incorrectly and will change to `PREFETCHT2` in the future.
     PREFETCH2,
 //    XCHG,
     POPF,
@@ -2980,7 +2993,7 @@ impl Opcode {
     }
 
     /// get the [`ConditionCode`] for this instruction, if it is in fact conditional. x86's
-    /// conditional instructions are `Jcc`, `CMOVcc`, andd `SETcc`.
+    /// conditional instructions are `Jcc`, `CMOVcc`, and `SETcc`.
     pub fn condition(&self) -> Option<ConditionCode> {
         match self {
             Opcode::JO |
-- 
cgit v1.1