From ed5c76a0f8e92656539f305b9b7ea5e032517f36 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 10 Oct 2021 14:40:55 -0700
Subject: support endbr{32,64}

---
 src/long_mode/mod.rs | 36 ++++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

(limited to 'src/long_mode/mod.rs')

diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 3d6d977..866eb8f 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -2139,6 +2139,8 @@ pub enum Opcode {
     SETSSBSY,
     CLRSSBSY,
     RSTORSSP,
+    ENDBR64,
+    ENDBR32,
 
     // TDX
     TDCALL,
@@ -4986,9 +4988,7 @@ enum OperandCode {
     ModRM_0x0f73 = OperandCodeBuilder::new().read_modrm().special_case(57).bits(),
     ModRM_0xf20f78 = OperandCodeBuilder::new().read_modrm().special_case(58).bits(),
     ModRM_0x660f78 = OperandCodeBuilder::new().read_modrm().special_case(59).bits(),
-//    ModRM_0x660f12 = OperandCodeBuilder::new().read_modrm().special_case(58).bits(),
-//    ModRM_0x660f16 = OperandCodeBuilder::new().read_modrm().special_case(59).bits(),
-//    ModRM_0x660f71 = OperandCodeBuilder::new().read_modrm().special_case(60).bits(),
+    ModRM_0xf30f1e = OperandCodeBuilder::new().special_case(60).bits(),
 //    ModRM_0x660f72 = OperandCodeBuilder::new().read_modrm().special_case(61).bits(),
 //    ModRM_0x660f73 = OperandCodeBuilder::new().read_modrm().special_case(62).bits(),
 //    ModRM_0x660fc7 = OperandCodeBuilder::new().read_modrm().special_case(63).bits(),
@@ -6372,7 +6372,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {
             0x1b => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev),
             0x1c => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev),
             0x1d => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev),
-            0x1e => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev),
+            0x1e => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::ModRM_0xf30f1e),
             0x1f => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev),
 
             0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0),
@@ -8833,6 +8833,34 @@ fn unlikely_operands<
             instruction.operand_count = 3;
 
         }
+        OperandCode::ModRM_0xf30f1e => {
+            let modrm = read_modrm(words)?;
+            match modrm {
+                0xfa => {
+                    instruction.opcode = Opcode::ENDBR64;
+                    instruction.operand_count = 0;
+                },
+                0xfb => {
+                    instruction.opcode = Opcode::ENDBR32;
+                    instruction.operand_count = 0;
+                },
+                _ => {
+                    let (sz, bank) = if instruction.prefixes.rex_unchecked().w() {
+                        (8, RegisterBank::Q)
+                    } else if !instruction.prefixes.operand_size() {
+                        (4, RegisterBank::D)
+                    } else {
+                        (2, RegisterBank::W)
+                    };
+                    instruction.operands[1] = OperandSpec::RegRRR;
+                    instruction.operands[0] = read_E(words, instruction, modrm, sz, sink)?;
+                    instruction.regs[0] =
+                        RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex_unchecked().r(), bank);
+                    instruction.operand_count = 2;
+
+                }
+            };
+        }
         OperandCode::G_E_xmm_Ub => {
             let modrm = read_modrm(words)?;
 
-- 
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