From 6eb2af6a3aba7bfad21775319c3a200c5c723918 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 3 May 2026 17:48:14 +0000
Subject: actually support avx/f16c in per-uarch decoding

---
 src/long_mode/uarch.rs | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/long_mode/uarch.rs')

diff --git a/src/long_mode/uarch.rs b/src/long_mode/uarch.rs
index 63fa972..9cfc9de 100644
--- a/src/long_mode/uarch.rs
+++ b/src/long_mode/uarch.rs
@@ -145,6 +145,7 @@ pub mod amd {
             .with_rdrand()
             .with_rdseed()
             .with_fma3()
+            .with_f16c()
 
             .with_xsavec()
             .with_xsaves()
@@ -272,6 +273,7 @@ pub mod intel {
             .with_abm()
             .with_fma3()
             .with_avx2()
+            .with_f16c()
     }
 
     /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores
-- 
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