From 2e34ef39d75caeb10c499712bc28ac9de8abf984 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sat, 3 Jul 2021 13:38:48 -0700
Subject: prefixes on 0f01-series opcodes are more strict

---
 src/long_mode/mod.rs | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

(limited to 'src/long_mode')

diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index b00a9ff..0cae4f0 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -9202,6 +9202,9 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                 if mod_bits == 0b11 {
                     instruction.operands[0] = OperandSpec::Nothing;
                     instruction.operand_count = 0;
+                    if instruction.prefixes.rep() || instruction.prefixes.repnz() {
+                        return Err(DecodeError::InvalidOpcode);
+                    }
                     if instruction.prefixes.operand_size() {
                         match m {
                             0b100 => {
@@ -9221,9 +9224,6 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                             }
                         }
                     } else {
-                        if instruction.prefixes.rep() || instruction.prefixes.repnz() {
-                            return Err(DecodeError::InvalidOpcode);
-                        }
                         match m {
                             0b000 => {
                                 instruction.opcode = Opcode::MONITOR;
@@ -9255,6 +9255,10 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                 let mod_bits = modrm >> 6;
                 let m = modrm & 7;
                 if mod_bits == 0b11 {
+                    if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() {
+                        return Err(DecodeError::InvalidOperand);
+                    }
+
                     instruction.operands[0] = OperandSpec::Nothing;
                     instruction.operand_count = 0;
                     match m {
@@ -9290,6 +9294,10 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                 let mod_bits = modrm >> 6;
                 let m = modrm & 7;
                 if mod_bits == 0b11 {
+                    if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() {
+                        return Err(DecodeError::InvalidOperand);
+                    }
+
                     match m {
                         0b000 => {
                             instruction.opcode = Opcode::VMRUN;
@@ -9495,6 +9503,10 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                         instruction.regs[0] = RegSpec::ecx();
                         instruction.operand_count = 1;
                     } else if m == 6 {
+                        if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() {
+                            return Err(DecodeError::InvalidOperand);
+                        }
+
                         instruction.opcode = Opcode::INVLPGB;
                         instruction.operand_count = 3;
                         instruction.operands[0] = OperandSpec::RegRRR;
@@ -9504,6 +9516,10 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
                         instruction.regs[1] = RegSpec::edx();
                         instruction.regs[3] = RegSpec::ecx();
                     } else if m == 7 {
+                        if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() {
+                            return Err(DecodeError::InvalidOperand);
+                        }
+
                         instruction.opcode = Opcode::TLBSYNC;
                         instruction.operand_count = 0;
                     } else {
-- 
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