From 2e34ef39d75caeb10c499712bc28ac9de8abf984 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 3 Jul 2021 13:38:48 -0700 Subject: prefixes on 0f01-series opcodes are more strict --- src/long_mode/mod.rs | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'src/long_mode') diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index b00a9ff..0cae4f0 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -9202,6 +9202,9 @@ fn unlikely_operands::Address, { @@ -9221,9 +9224,6 @@ fn unlikely_operands::Address, { instruction.opcode = Opcode::MONITOR; @@ -9255,6 +9255,10 @@ fn unlikely_operands::Address, > 6; let m = modrm & 7; if mod_bits == 0b11 { + if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { + return Err(DecodeError::InvalidOperand); + } + instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match m { @@ -9290,6 +9294,10 @@ fn unlikely_operands::Address, > 6; let m = modrm & 7; if mod_bits == 0b11 { + if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { + return Err(DecodeError::InvalidOperand); + } + match m { 0b000 => { instruction.opcode = Opcode::VMRUN; @@ -9495,6 +9503,10 @@ fn unlikely_operands::Address, ::Address,