From 33c520341b373ac18e7924eb9227615ac65c2618 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 22 Feb 2020 00:51:30 -0800 Subject: support 660f sse2 instructions this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand --- src/long_mode/display.rs | 58 ++++++++++ src/long_mode/mod.rs | 284 ++++++++++++++++++++++++++++++++--------------- 2 files changed, 254 insertions(+), 88 deletions(-) (limited to 'src/long_mode') diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index be7ab0d..d45a98a 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -285,7 +285,9 @@ impl fmt::Display for Opcode { &Opcode::CMPSS => write!(f, "cmpss"), &Opcode::CMPSD => write!(f, "cmpsd"), &Opcode::UNPCKLPS => write!(f, "unpcklps"), + &Opcode::UNPCKLPD => write!(f, "unpcklpd"), &Opcode::UNPCKHPS => write!(f, "unpckhps"), + &Opcode::UNPCKHPD => write!(f, "unpckhpd"), &Opcode::MOVUPS => write!(f, "movups"), &Opcode::MOVQ2DQ => write!(f, "movq2dq"), &Opcode::MOVDQ2Q => write!(f, "movdq2q"), @@ -499,40 +501,61 @@ impl fmt::Display for Opcode { &Opcode::SETLE => write!(f, "setle"), &Opcode::SETG => write!(f, "setg"), &Opcode::ADDPS => write!(f, "addps"), + &Opcode::ADDPD => write!(f, "addpd"), &Opcode::ANDNPS => write!(f, "andnps"), + &Opcode::ANDNPD => write!(f, "andnpd"), &Opcode::ANDPS => write!(f, "andps"), + &Opcode::ANDPD => write!(f, "andpd"), &Opcode::BSWAP => write!(f, "bswap"), &Opcode::CMPPS => write!(f, "cmpps"), + &Opcode::CMPPD => write!(f, "cmppd"), + &Opcode::COMISD => write!(f, "comisd"), &Opcode::COMISS => write!(f, "comiss"), &Opcode::CVTDQ2PS => write!(f, "cvtdq2ps"), + &Opcode::CVTPS2DQ => write!(f, "cvtps2dq"), &Opcode::CVTPI2PS => write!(f, "cvtpi2ps"), &Opcode::CVTPI2PD => write!(f, "cvtpi2pd"), &Opcode::CVTPS2PD => write!(f, "cvtps2pd"), + &Opcode::CVTPD2PS => write!(f, "cvtpd2ps"), &Opcode::CVTPS2PI => write!(f, "cvtps2pi"), + &Opcode::CVTPD2PI => write!(f, "cvtpd2pi"), &Opcode::CVTTPS2PI => write!(f, "cvttps2pi"), + &Opcode::CVTTPD2PI => write!(f, "cvttpd2pi"), + &Opcode::CVTTPD2DQ => write!(f, "cvttpd2dq"), &Opcode::DIVPS => write!(f, "divps"), + &Opcode::DIVPD => write!(f, "divpd"), &Opcode::EMMS => write!(f, "emms"), &Opcode::GETSEC => write!(f, "getsec"), &Opcode::LFS => write!(f, "lfs"), &Opcode::LGS => write!(f, "lgs"), &Opcode::LSS => write!(f, "lss"), &Opcode::MASKMOVQ => write!(f, "maskmovq"), + &Opcode::MASKMOVDQU => write!(f, "maskmovdqu"), &Opcode::MAXPS => write!(f, "maxps"), + &Opcode::MAXPD => write!(f, "maxpd"), &Opcode::MINPS => write!(f, "minps"), + &Opcode::MINPD => write!(f, "minpd"), &Opcode::MOVAPS => write!(f, "movaps"), &Opcode::MOVAPD => write!(f, "movapd"), &Opcode::MOVD => write!(f, "movd"), &Opcode::MOVLPS => write!(f, "movlps"), + &Opcode::MOVLPD => write!(f, "movlpd"), &Opcode::MOVLHPS => write!(f, "movlhps"), &Opcode::MOVHPS => write!(f, "movhps"), + &Opcode::MOVHPD => write!(f, "movhpd"), &Opcode::MOVHLPS => write!(f, "movhlps"), &Opcode::MOVUPD => write!(f, "movupd"), &Opcode::MOVMSKPS => write!(f, "movmskps"), + &Opcode::MOVMSKPD => write!(f, "movmskpd"), &Opcode::MOVNTI => write!(f, "movnti"), &Opcode::MOVNTPS => write!(f, "movntps"), + &Opcode::MOVNTPD => write!(f, "movntpd"), &Opcode::MOVNTQ => write!(f, "movntq"), + &Opcode::MOVNTDQ => write!(f, "movntdq"), &Opcode::MULPS => write!(f, "mulps"), + &Opcode::MULPD => write!(f, "mulpd"), &Opcode::ORPS => write!(f, "orps"), + &Opcode::ORPD => write!(f, "orpd"), &Opcode::PACKSSDW => write!(f, "packssdw"), &Opcode::PACKSSWB => write!(f, "packsswb"), &Opcode::PACKUSWB => write!(f, "packuswb"), @@ -601,17 +624,22 @@ impl fmt::Display for Opcode { &Opcode::RSM => write!(f, "rsm"), &Opcode::RSQRTPS => write!(f, "rsqrtps"), &Opcode::SHLD => write!(f, "shld"), + &Opcode::SHUFPD => write!(f, "shufpd"), &Opcode::SHUFPS => write!(f, "shufps"), &Opcode::SLHD => write!(f, "slhd"), &Opcode::SQRTPS => write!(f, "sqrtps"), + &Opcode::SQRTPD => write!(f, "sqrtpd"), &Opcode::SUBPS => write!(f, "subps"), + &Opcode::SUBPD => write!(f, "subpd"), &Opcode::SYSENTER => write!(f, "sysenter"), &Opcode::SYSEXIT => write!(f, "sysexit"), + &Opcode::UCOMISD => write!(f, "ucomisd"), &Opcode::UCOMISS => write!(f, "ucomiss"), &Opcode::UD2E => write!(f, "ud2e"), &Opcode::VMREAD => write!(f, "vmread"), &Opcode::VMWRITE => write!(f, "vmwrite"), &Opcode::XORPS => write!(f, "xorps"), + &Opcode::XORPD => write!(f, "xorpd"), &Opcode::CBW => write!(f, "cbw"), &Opcode::CWDE => write!(f, "cwde"), &Opcode::CDQE => write!(f, "cdqe"), @@ -623,6 +651,7 @@ impl fmt::Display for Opcode { &Opcode::BLSI => write!(f, "blsi"), &Opcode::BLSMSK => write!(f, "blsmsk"), &Opcode::BLSR => write!(f, "blsr"), + &Opcode::VMCLEAR => write!(f, "vmclear"), &Opcode::VMCALL => write!(f, "vmcall"), &Opcode::VMLAUNCH => write!(f, "vmlaunch"), &Opcode::VMRESUME => write!(f, "vmresume"), @@ -1291,12 +1320,19 @@ impl > Colorize> Colorize { write!(out, "{}", colors.arithmetic_op(self)) } Opcode::POPF | @@ -1553,33 +1593,44 @@ impl > Colorize> Colorize> Colorize> Colorize { write!(out, "{}", colors.comparison_op(self)) } Opcode::WRMSR | @@ -1797,6 +1854,7 @@ impl > Colorize>(bytes_iter: &mut T, length: &mut u8) -> Result<(OpcodeRecord, u8), DecodeError> { @@ -5138,6 +5177,15 @@ fn read_operands>(decoder: &InstDecoder, mut bytes_iter: T, instruction.modrm_mmm.num &= 0b111; instruction.operand_count = 2; }, + OperandCode::G_U_xmm => { + instruction.operands[1] = mem_oper; + instruction.modrm_rrr.bank = RegisterBank::X; + if mem_oper != OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.modrm_mmm.bank = RegisterBank::X; + instruction.operand_count = 2; + }, op @ OperandCode::G_M_xmm | op @ OperandCode::G_E_xmm => { instruction.modrm_rrr.bank = RegisterBank::X; @@ -5158,7 +5206,8 @@ fn read_operands>(decoder: &InstDecoder, mut bytes_iter: T, let modrm = read_modrm(&mut bytes_iter, length)?; instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; - instruction.modrm_rrr = RegSpec { bank: RegisterBank::X, num: (modrm >> 3) & 7 }; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.imm = read_num(&mut bytes_iter, 1)? as u8 as u64; @@ -5379,6 +5428,36 @@ fn unlikely_operands>(decoder: &InstDecoder, mut bytes_iter instruction.imm = read_imm_signed(&mut bytes_iter, 1, length)? as u64; instruction.operands[1] = OperandSpec::ImmU8; }, + OperandCode::ModRM_0x660f12 => { + // If this is reg-reg, interpret the instruction as 66-prefixed (no-op here) + // `movhlps`. If this is reg-mem, it's a `movlpd`. + let modrm = read_modrm(&mut bytes_iter, length)?; + if modrm & 0xc0 == 0xc0 { + instruction.opcode = Opcode::MOVHLPS; + } else { + instruction.opcode = Opcode::MOVLPD; + } + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + instruction.operand_count = 2; + } + OperandCode::ModRM_0x660f16 => { + // If this is reg-reg, interpret the instruction as 66-prefixed (no-op here) + // `movlhps`. If this is reg-mem, it's a `movhpd`. + let modrm = read_modrm(&mut bytes_iter, length)?; + if modrm & 0xc0 == 0xc0 { + instruction.opcode = Opcode::MOVLHPS; + } else { + instruction.opcode = Opcode::MOVHPD; + } + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + instruction.operand_count = 2; + } OperandCode::ModRM_0x660f38 => { let op = bytes_iter.next().ok_or(DecodeError::ExhaustedInput).map(|b| { *length += 1; b })?; match op { @@ -5517,6 +5596,24 @@ fn unlikely_operands>(decoder: &InstDecoder, mut bytes_iter instruction.imm = read_imm_signed(&mut bytes_iter, 1, length)? as u64; instruction.operands[1] = OperandSpec::ImmU8; }, + OperandCode::ModRM_0x660fc7 => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + let r = (modrm >> 3) & 7; + match r { + 6 => { + instruction.opcode = Opcode::VMCLEAR; + instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 1 /* doesn't matter, something using this width is invalid */, length)?; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.operand_count = 1; + } + _ => { + return Err(DecodeError::InvalidOpcode); + } + } + }, OperandCode::G_mm_Edq => { instruction.operands[1] = mem_oper; instruction.modrm_rrr.bank = RegisterBank::MM; @@ -5581,6 +5678,17 @@ fn unlikely_operands>(decoder: &InstDecoder, mut bytes_iter } } }, + OperandCode::G_xmm_Ed_Ib => { + instruction.operands[1] = mem_oper; + instruction.operands[2] = OperandSpec::ImmU8; + instruction.imm = + read_num(&mut bytes_iter, 1)? as u64; + *length += 1; + instruction.modrm_rrr.bank = RegisterBank::X; + if mem_oper == OperandSpec::RegMMM { + instruction.modrm_mmm.bank = RegisterBank::D; + } + }, OperandCode::G_xmm_Eq => { instruction.operands[1] = mem_oper; instruction.modrm_rrr.bank = RegisterBank::X; -- cgit v1.1