From 340d89e4efd6200e733db8f67e787a6625a0a128 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 18 May 2026 07:06:50 +0000
Subject: adapt long-mode behavior support to protected mode and real mode

along the way, fix an error: maskmov is memory read-write.
additionally, operand information about {push,pop}a{,d}.
---
 src/long_mode/behavior.rs | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

(limited to 'src/long_mode')

diff --git a/src/long_mode/behavior.rs b/src/long_mode/behavior.rs
index dbadd29..3e1b4a7 100644
--- a/src/long_mode/behavior.rs
+++ b/src/long_mode/behavior.rs
@@ -2938,12 +2938,17 @@ static CMPXCHG16B_OPS: &'static [ImplicitOperand] = &[
     },
 ];
 
-// TODO: register size should be picked by memory access size, but defaulting to rdi for now.
 static MASKMOVQ_OPS: &'static [ImplicitOperand] = &[
     ImplicitOperand {
         spec: OperandSpec::Deref,
         reg: RegSpec::rdi(),
         disp: 0i32,
+        write: false,
+    },
+    ImplicitOperand {
+        spec: OperandSpec::Deref,
+        reg: RegSpec::rdi(),
+        disp: 0i32,
         write: true,
     },
 ];
@@ -3003,6 +3008,12 @@ static EDI_MEMWRITE_OPS: &'static [ImplicitOperand] = &[
         disp: 0i32,
         write: false,
     },
+    ImplicitOperand {
+        spec: OperandSpec::Deref,
+        reg: RegSpec::edi(),
+        disp: 0i32,
+        write: true,
+    },
 ];
 
 static RDI_MEMWRITE_OPS: &'static [ImplicitOperand] = &[
@@ -3012,6 +3023,12 @@ static RDI_MEMWRITE_OPS: &'static [ImplicitOperand] = &[
         disp: 0i32,
         write: false,
     },
+    ImplicitOperand {
+        spec: OperandSpec::Deref,
+        reg: RegSpec::rdi(),
+        disp: 0i32,
+        write: true,
+    },
 ];
 
 static PCMPESTRI_64B_OPS: &'static [ImplicitOperand] = &[
@@ -3538,6 +3555,7 @@ fn behavior_table_size_is_right() {
     assert_eq!(TABLE.len(), super::Opcode::COUNT);
 
     assert_eq!(opcode2behavior(&Opcode::VMOVLHPS), GENERAL_W_R_R);
+    assert_eq!(opcode2behavior(&Opcode::FDIVRP), GENERAL_RW_R);
 }
 
 /// this table MUST line up with Opcode declaration order in `mod.rs`.
@@ -4978,6 +4996,8 @@ static TABLE: [BehaviorDigest; 1413] = [
         // TODO: x87 stack pointer dec
     /* FDECSTP => */ BehaviorDigest::empty()
             .set_pl_any(),
+    /* FDISI8087_NOP => */ BehaviorDigest::empty()
+            .set_pl_any(),
     /* FDIV => */ GENERAL_RW_R,
         // TODO: x87 stack pop
     /* FDIVP => */ GENERAL_RW_R,
@@ -4986,8 +5006,6 @@ static TABLE: [BehaviorDigest; 1413] = [
     /* FDIVRP => */ GENERAL_RW_R,
     /* FENI8087_NOP => */ BehaviorDigest::empty()
             .set_pl_any(),
-    /* FDISI8087_NOP => */ BehaviorDigest::empty()
-            .set_pl_any(),
         // TODO: the behavior here is ... inaccurate. st(i) is not read, but state associated with
         // that register is modified. so it's kind of read?
     /* FFREE => */ BehaviorDigest::empty()
-- 
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