From 620f731301009349aae40f0b172b463fbb6556e7 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sat, 3 Jul 2021 13:38:01 -0700
Subject: add hreset

---
 src/long_mode/display.rs |  4 ++++
 src/long_mode/mod.rs     | 25 +++++++++++++++++++++++--
 2 files changed, 27 insertions(+), 2 deletions(-)

(limited to 'src/long_mode')

diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs
index 5f74a3e..b9e4a92 100644
--- a/src/long_mode/display.rs
+++ b/src/long_mode/display.rs
@@ -1350,6 +1350,9 @@ const MNEMONICS: &[&'static str] = &[
     "encodekey256",
     "loadiwkey",
 
+    // unsure
+    "hreset",
+
     // 3dnow
     "femms",
     "pi2fw",
@@ -3202,6 +3205,7 @@ impl <T: fmt::Write, Y: YaxColors> Colorize<T, Y> for Opcode {
             Opcode::ENCODEKEY128 |
             Opcode::ENCODEKEY256 |
             Opcode::LOADIWKEY |
+            Opcode::HRESET |
             Opcode::WRUSS |
             Opcode::WRSS |
             Opcode::INCSSP |
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 254ccc7..b00a9ff 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -585,7 +585,7 @@ impl Operand {
             OperandSpec::Nothing => {
                 Operand::Nothing
             }
-            // the register in regs[0]
+            // the register in modrm_rrr
             OperandSpec::RegRRR => {
                 Operand::Register(inst.regs[0])
             }
@@ -2067,6 +2067,9 @@ pub enum Opcode {
     ENCODEKEY256,
     LOADIWKEY,
 
+    // unsure
+    HRESET,
+
     // 3dnow
     FEMMS,
     PI2FW,
@@ -4828,6 +4831,7 @@ enum OperandCode {
     ModRM_0xf30f38df = OperandCodeBuilder::new().read_modrm().special_case(49).bits(),
     ModRM_0xf30f38fa = OperandCodeBuilder::new().read_modrm().special_case(50).bits(),
     ModRM_0xf30f38fb = OperandCodeBuilder::new().read_modrm().special_case(51).bits(),
+    ModRM_0xf30f3af0 = OperandCodeBuilder::new().read_modrm().special_case(52).bits(),
 //    ModRM_0x660f3a = OperandCodeBuilder::new().read_modrm().special_case(52).bits(),
 //    ModRM_0x0f38 = OperandCodeBuilder::new().read_modrm().special_case(53).bits(),
 //    ModRM_0x0f3a = OperandCodeBuilder::new().read_modrm().special_case(54).bits(),
@@ -6933,7 +6937,14 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {
 }
 
 fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {
-    if prefixes.rep() || prefixes.repnz() {
+    if prefixes.rep() {
+        return match opcode {
+            0xf0 => OpcodeRecord(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0),
+            _ => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+        };
+    }
+
+    if prefixes.repnz() {
         return OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing);
     }
 
@@ -8707,6 +8718,16 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
             instruction.regs[0].bank = RegisterBank::D;
             instruction.regs[1].bank = RegisterBank::D;
         }
+        OperandCode::ModRM_0xf30f3af0 => {
+            let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
+            if modrm & 0xc0 != 0xc0 {
+                return Err(DecodeError::InvalidOpcode);
+                // invalid
+            }
+            instruction.opcode = Opcode::HRESET;
+            instruction.imm = read_num(words, 1)?;
+            instruction.operands[0] = OperandSpec::ImmU8;
+        }
         OperandCode::G_mm_Edq => {
             instruction.regs[0].bank = RegisterBank::MM;
             instruction.regs[0].num &= 0b111;
-- 
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