From 876fc7449cf862e7ffe788885fb7d4209ad2eb5d Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 3 May 2020 13:54:02 -0700 Subject: add width() to ask width of an x86 operand this is largely wrong for memory operands, which require more invasive changes --- src/long_mode/mod.rs | 106 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) (limited to 'src/long_mode') diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 3319141..05eee0a 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -179,6 +179,21 @@ impl RegSpec { } #[inline] + pub fn ecx() -> RegSpec { + RegSpec { bank: RegisterBank::D, num: 1 } + } + + #[inline] + pub fn edx() -> RegSpec { + RegSpec { bank: RegisterBank::D, num: 2 } + } + + #[inline] + pub fn ebx() -> RegSpec { + RegSpec { bank: RegisterBank::D, num: 3 } + } + + #[inline] pub fn ax() -> RegSpec { RegSpec { bank: RegisterBank::W, num: 0 } } @@ -197,6 +212,66 @@ impl RegSpec { pub fn cl() -> RegSpec { RegSpec { bank: RegisterBank::B, num: 1 } } + + #[inline] + pub fn ah() -> RegSpec { + RegSpec { bank: RegisterBank::B, num: 4 } + } + + #[inline] + pub fn ch() -> RegSpec { + RegSpec { bank: RegisterBank::B, num: 5 } + } + + #[inline] + pub fn width(&self) -> u8 { + match self.bank { + RegisterBank::Q => 8, + RegisterBank::D => 4, + RegisterBank::W => 2, + RegisterBank::B | + RegisterBank::rB => { + 1 + }, + RegisterBank::CR | + RegisterBank::DR => { + 8 + }, + RegisterBank::S => { + 2 + }, + RegisterBank::EIP => { + 4 + } + RegisterBank::RIP => { + 8 + } + RegisterBank::EFlags => { + 4 + } + RegisterBank::RFlags => { + 8 + } + RegisterBank::X => { + 16 + } + RegisterBank::Y => { + 32 + } + RegisterBank::Z => { + 64 + } + RegisterBank::ST => { + 10 + } + RegisterBank::MM => { + 8 + } + RegisterBank::K => { + 8 + } + } + } } #[allow(non_camel_case_types)] @@ -361,6 +436,37 @@ impl Operand { } } } + + pub fn width(&self) -> u8 { + match self { + Operand::Nothing => { + panic!("non-operand does not have a size"); + } + Operand::Register(reg) => { + reg.width() + } + Operand::ImmediateI8(_) | + Operand::ImmediateU8(_) => { + 1 + } + Operand::ImmediateI16(_) | + Operand::ImmediateU16(_) => { + 2 + } + Operand::ImmediateI32(_) | + Operand::ImmediateU32(_) => { + 4 + } + Operand::ImmediateI64(_) | + Operand::ImmediateU64(_) => { + 8 + } + // memory operands + _ => { + 8 + } + } + } } #[test] -- cgit v1.1