From 7f0429ad45f748b58658ba41420ca1d0f3784f48 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Mon, 28 Jun 2021 22:14:17 -0700
Subject: round out x86_32 support - avx2, avx, memory sizes

---
 src/protected_mode/mod.rs | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

(limited to 'src/protected_mode/mod.rs')

diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 971d7a6..060511b 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -3685,6 +3685,8 @@ impl InstDecoder {
             Opcode::VPCMPGTD |
             Opcode::VPCMPGTQ |
             Opcode::VPCMPGTW |
+            Opcode::VPCMPESTRI |
+            Opcode::VPCMPESTRM |
             Opcode::VPCMPISTRI |
             Opcode::VPCMPISTRM |
             Opcode::VPERM2F128 |
@@ -7583,10 +7585,10 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
                 return Err(DecodeError::InvalidOperand);
             }
             if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) {
-                if instruction.prefixes.vex().w() {
-                    instruction.mem_size = 6;
-                } else {
+                if instruction.prefixes.operand_size() {
                     instruction.mem_size = 4;
+                } else {
+                    instruction.mem_size = 6;
                 }
             } else if [Opcode::ENQCMD, Opcode::ENQCMDS].contains(&instruction.opcode) {
                 instruction.mem_size = 64;
@@ -7616,6 +7618,11 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
                 instruction.modrm_rrr = RegSpec::from_parts((modrm >> 3) & 7, if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D });
                 instruction.operands[0] = OperandSpec::RegRRR;
                 instruction.operands[1] = read_M(&mut bytes_iter, instruction, modrm, length)?;
+                if instruction.prefixes.operand_size() {
+                    instruction.mem_size = 4;
+                } else {
+                    instruction.mem_size = 6;
+                }
             }
         },
         OperandCode::ModRM_0xc5 => {
@@ -7640,6 +7647,11 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
                 instruction.modrm_rrr = RegSpec::from_parts((modrm >> 3) & 7, if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D });
                 instruction.operands[0] = OperandSpec::RegRRR;
                 instruction.operands[1] = read_M(&mut bytes_iter, instruction, modrm, length)?;
+                if instruction.prefixes.operand_size() {
+                    instruction.mem_size = 4;
+                } else {
+                    instruction.mem_size = 6;
+                }
             }
         },
         OperandCode::G_U_xmm_Ub => {
-- 
cgit v1.1