From 48559b18574b44e2de879a5c641ab602ec22f0d8 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 4 Jul 2021 12:20:13 -0700
Subject: fix several incorrect tests and docs in 64- and 32-bit modes

---
 src/protected_mode/vex.rs | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

(limited to 'src/protected_mode/vex.rs')

diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs
index 053d1aa..3550f77 100644
--- a/src/protected_mode/vex.rs
+++ b/src/protected_mode/vex.rs
@@ -412,7 +412,7 @@ fn read_vex_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
             instruction.opcode = if modrm & 0xc0 == 0xc0 {
                 Opcode::VMOVHLPS
             } else {
-                instruction.mem_size = 4;
+                instruction.mem_size = 8;
                 Opcode::VMOVLPS
             };
             instruction.regs[0] =
@@ -1854,7 +1854,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
                         } else {
                             VEXOperandCode::G_V_E_xmm
                         }),
-                        0xDA => (Opcode::VPMINSW, if L {
+                        0xDA => (Opcode::VPMINUB, if L {
                             VEXOperandCode::G_V_E_ymm
                         } else {
                             VEXOperandCode::G_V_E_xmm
@@ -3130,12 +3130,12 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
                         VEXOperandCode::G_E_xmm_imm8
                     }),
                     0x0A => (Opcode::VROUNDSS, if L {
-                        VEXOperandCode::G_V_E_ymm_imm8
+                        VEXOperandCode::G_V_E_xmm_imm8
                     } else {
                         VEXOperandCode::G_V_E_xmm_imm8
                     }),
                     0x0B => (Opcode::VROUNDSD, if L {
-                        VEXOperandCode::G_V_E_ymm_imm8
+                        VEXOperandCode::G_V_E_xmm_imm8
                     } else {
                         VEXOperandCode::G_V_E_xmm_imm8
                     }),
@@ -3171,14 +3171,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
                     } else {
                         VEXOperandCode::Ev_G_xmm_imm8
                     }),
-                    0x16 => if instruction.prefixes.vex_unchecked().w() {
-                        (Opcode::VPEXTRQ, if L {
-                            instruction.opcode = Opcode::Invalid;
-                            return Err(DecodeError::InvalidOpcode);
-                        } else {
-                            VEXOperandCode::Ev_G_xmm_imm8
-                        })
-                    } else {
+                    0x16 => {
                         (Opcode::VPEXTRD, if L {
                             instruction.opcode = Opcode::Invalid;
                             return Err(DecodeError::InvalidOpcode);
@@ -3198,7 +3191,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
                         return Err(DecodeError::InvalidOpcode);
                     } else {
                         (Opcode::VINSERTF128, if L {
-                            VEXOperandCode::G_V_E_ymm_imm8
+                            VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8
                         } else {
                             instruction.opcode = Opcode::Invalid;
                             return Err(DecodeError::InvalidOpcode);
@@ -3232,14 +3225,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
                     } else {
                         VEXOperandCode::G_V_E_xmm_imm8
                     }),
-                    0x22 => if instruction.prefixes.vex_unchecked().w() {
-                        (Opcode::VPINSRQ, if L {
-                            instruction.opcode = Opcode::Invalid;
-                            return Err(DecodeError::InvalidOpcode);
-                        } else {
-                            VEXOperandCode::G_V_xmm_Ev_imm8
-                        })
-                    } else {
+                    0x22 => {
                         (Opcode::VPINSRD, if L {
                             instruction.opcode = Opcode::Invalid;
                             return Err(DecodeError::InvalidOpcode);
-- 
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