From 7e154da8e2bd7b8892bdefe2f71c111c2135b0a3 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 3 Jul 2021 15:51:22 -0700 Subject: be more strict about denying invalid operands --- src/protected_mode/mod.rs | 2 +- src/protected_mode/vex.rs | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/protected_mode') diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs index c9ba9f2..589d7a3 100644 --- a/src/protected_mode/mod.rs +++ b/src/protected_mode/mod.rs @@ -6868,7 +6868,7 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { - if prefixes.operand_size() || prefixes.repnz() { + if prefixes != &Prefixes::new(0x10) { return OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); } return match opcode { diff --git a/src/protected_mode/vex.rs b/src/protected_mode/vex.rs index 7c55ef1..36ccc66 100644 --- a/src/protected_mode/vex.rs +++ b/src/protected_mode/vex.rs @@ -1528,7 +1528,11 @@ fn read_vex_instruction::Address, (Opcode::VMOVHPD, VEXOperandCode::G_V_M_xmm), + 0x16 => (Opcode::VMOVHPD, if L { + return Err(DecodeError::InvalidOpcode); + } else { + VEXOperandCode::G_V_M_xmm + }), 0x17 => (Opcode::VMOVHPD, if L { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOpcode); -- cgit v1.1