From 876fc7449cf862e7ffe788885fb7d4209ad2eb5d Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 3 May 2020 13:54:02 -0700
Subject: add width() to ask width of an x86 operand

this is largely wrong for memory operands, which require more invasive changes
---
 src/protected_mode/mod.rs | 85 ++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 81 insertions(+), 4 deletions(-)

(limited to 'src/protected_mode')

diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 2a32a91..76af3a1 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -145,13 +145,13 @@ impl RegSpec {
     }
 
     #[inline]
-    pub fn bx() -> RegSpec {
-        RegSpec { bank: RegisterBank::W, num: 3 }
+    pub fn ebx() -> RegSpec {
+        RegSpec { bank: RegisterBank::D, num: 3 }
     }
 
     #[inline]
-    pub fn ebx() -> RegSpec {
-        RegSpec { bank: RegisterBank::D, num: 3 }
+    pub fn bx() -> RegSpec {
+        RegSpec { bank: RegisterBank::W, num: 3 }
     }
 
     #[inline]
@@ -193,6 +193,56 @@ impl RegSpec {
     pub fn cl() -> RegSpec {
         RegSpec { bank: RegisterBank::B, num: 1 }
     }
+
+    #[inline]
+    pub fn ah() -> RegSpec {
+        RegSpec { bank: RegisterBank::B, num: 4 }
+    }
+
+    #[inline]
+    pub fn ch() -> RegSpec {
+        RegSpec { bank: RegisterBank::B, num: 5 }
+    }
+
+    #[inline]
+    pub fn width(&self) -> u8 {
+        match self.bank {
+            RegisterBank::D => 4,
+            RegisterBank::W => 2,
+            RegisterBank::B => 1,
+            RegisterBank::CR |
+            RegisterBank::DR => {
+                4
+            },
+            RegisterBank::S => {
+                2
+            },
+            RegisterBank::EIP => {
+                4
+            }
+            RegisterBank::EFlags => {
+                4
+            }
+            RegisterBank::X => {
+                16
+            }
+            RegisterBank::Y => {
+                32
+            }
+            RegisterBank::Z => {
+                64
+            }
+            RegisterBank::ST => {
+                10
+            }
+            RegisterBank::MM => {
+                8
+            }
+            RegisterBank::K => {
+                8
+            }
+        }
+    }
 }
 
 #[allow(non_camel_case_types)]
@@ -347,6 +397,33 @@ impl Operand {
             }
         }
     }
+
+    pub fn width(&self) -> u8 {
+        match self {
+            Operand::Nothing => {
+                panic!("non-operand does not have a size");
+            }
+            Operand::Register(reg) => {
+                reg.width()
+            }
+            Operand::ImmediateI8(_) |
+            Operand::ImmediateU8(_) => {
+                1
+            }
+            Operand::ImmediateI16(_) |
+            Operand::ImmediateU16(_) => {
+                2
+            }
+            Operand::ImmediateI32(_) |
+            Operand::ImmediateU32(_) => {
+                4
+            }
+            // memory operands
+            _ => {
+                4
+            }
+        }
+    }
 }
 
 #[test]
-- 
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