From 7bffc21711fcbeeb7b5a38d3297b9b060f54534d Mon Sep 17 00:00:00 2001 From: iximeow Date: Tue, 9 Jun 2026 07:52:20 +0000 Subject: fix vgatherdpd using incorrect simd vector width for gather indices --- src/real_mode/vex.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/real_mode/vex.rs') diff --git a/src/real_mode/vex.rs b/src/real_mode/vex.rs index 3a7fbe3..6a74fe8 100644 --- a/src/real_mode/vex.rs +++ b/src/real_mode/vex.rs @@ -1321,7 +1321,7 @@ fn read_vex_operands< instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; - if instruction.opcode == Opcode::VPGATHERDQ { + if instruction.opcode == Opcode::VPGATHERDQ || instruction.opcode == Opcode::VGATHERDPD { instruction.regs[2].bank = RegisterBank::X; } else { instruction.regs[2].bank = index_bank; -- cgit v1.1